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git://nv-tegra.nvidia.com/linux-nv-oot.git
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45eab8b2ae
MCB aperture is already ioremapped in MC driver using devm_ioremap_resource(). This doesn't allow other driver to ioremap this aperture using devm_ioremap* calls. mc-t26x driver need to access MCB aperture to get carveout info. So, fix this by using just ioremap on aperture without using devm* APIs. Also, fix the carveout apertures. Bug 4707077 Change-Id: Ie7426ad3519306dd4dffdf54e4c58e81f3c8fb34 Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3158697 Reviewed-by: Ketan Patil <ketanp@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
85 lines
2.1 KiB
C
85 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2023-2024 NVIDIA CORPORATION. All rights reserved.
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#define pr_fmt(fmt) "mc: " fmt
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#include <linux/module.h>
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#include <linux/export.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <soc/tegra/mc-t26x.h>
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#define MC_SECURITY_CARVEOUT_BASE 0xa004
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#define MC_CARVEOUT_NEXT 0xa0
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#define MC_SECURITY_CARVEOUT_LITE_BASE 0xb404
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#define MC_CARVEOUT_LITE_NEXT 0x60
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#define MC_CARVEOUT_BASE_HI 0x4
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#define MC_SECURITY_CARVEOUT_SIZE_128KB 0x8
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static void __iomem *mcb_base;
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static inline u32 mc_readl(unsigned long offset)
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{
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return readl_relaxed(mcb_base + offset);
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}
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int tegra264_mc_get_carveout_info(unsigned int id, phys_addr_t *base, u64 *size)
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{
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u32 offset;
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if (id < 1 || id > 42)
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return -EINVAL;
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if (id < 32)
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offset = MC_SECURITY_CARVEOUT_BASE + MC_CARVEOUT_NEXT * (id - 1);
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else
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offset = MC_SECURITY_CARVEOUT_LITE_BASE + MC_CARVEOUT_LITE_NEXT * (id - 32);
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*base = mc_readl(offset + 0x0);
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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*base |= (phys_addr_t)mc_readl(offset + MC_CARVEOUT_BASE_HI) << 32;
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#endif
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if (size)
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*size = (u64)mc_readl(offset + MC_SECURITY_CARVEOUT_SIZE_128KB) << 17;
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return 0;
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}
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EXPORT_SYMBOL(tegra264_mc_get_carveout_info);
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const struct of_device_id tegra_mc_of_ids[] = {
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{ .compatible = "nvidia,tegra-t26x-mc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, tegra_mc_of_ids);
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static int tegra_mc_probe(struct platform_device *pdev)
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{
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struct resource *r;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r)
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return PTR_ERR(r);
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mcb_base = ioremap(r->start, resource_size(r));
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if (IS_ERR_OR_NULL(mcb_base))
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return PTR_ERR(mcb_base);
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return 0;
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}
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static int tegra_mc_remove(struct platform_device *pdev)
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{
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iounmap(mcb_base);
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return 0;
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}
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static struct platform_driver mc_driver = {
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.driver = {
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.name = "nv-tegra-t26x-mc",
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.of_match_table = tegra_mc_of_ids,
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.owner = THIS_MODULE,
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},
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.remove = tegra_mc_remove,
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};
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module_platform_driver_probe(mc_driver, tegra_mc_probe);
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MODULE_AUTHOR("Ashish Mhetre <amhetre@nvidia.com>");
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MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
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MODULE_LICENSE("GPL v2");
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