mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 09:11:26 +03:00
4d81ee0f63
EMC clock is not intended to be managed by the kernel/ccplex. It is completely managed by the BPMP BWMGR driver. Remove outdated code that touches emc clock directly, and fix the NULL pointer dereference issue. Bug 5622903 Change-Id: Ied1b6aaceaa026f954917b4b46f47dece1521d62 Signed-off-by: Johnny Liu <johnliu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3487187 Reviewed-by: Chinniah Poosapadi <cpoosapadi@nvidia.com> Reviewed-by: Narendra Kondapalli <nkondapalli@nvidia.com> Reviewed-by: Shubham Chandra <shubhamc@nvidia.com> Reviewed-by: Akihiro Mizusawa <amizusawa@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com>
102 lines
2.6 KiB
C
102 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* SPDX-FileCopyrightText: Copyright (C) 2015-2025 NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef _TEGRA_CAMERA_PLATFORM_H_
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#define _TEGRA_CAMERA_PLATFORM_H_
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#include <uapi/media/tegra_camera_platform.h>
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/* avoid overflows */
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#define DEFAULT_PG_CLK_RATE (UINT_MAX - 1)
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/**
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* enum tegra_camera_hw_type - camera hw engines
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*/
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enum tegra_camera_hw_type {
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HWTYPE_NONE = 0,
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HWTYPE_CSI,
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HWTYPE_SLVSEC,
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HWTYPE_VI,
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HWTYPE_ISPA,
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HWTYPE_ISPB,
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HWTYPE_MAX,
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};
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/**
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* enum tegra_camera_sensor_type - camera sensor types
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*/
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enum tegra_camera_sensor_type {
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SENSORTYPE_NONE = 0,
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SENSORTYPE_DPHY,
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SENSORTYPE_CPHY,
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SENSORTYPE_SLVSEC,
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SENSORTYPE_VIRTUAL,
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/* HDMI-IN or other inputs */
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SENSORTYPE_OTHER,
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SENSORTYPE_MAX,
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};
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struct tegra_camera_dev_info;
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/**
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* struct tegra_camera_dev_ops - camera device operations
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* @set_rate: set the device clock rate
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*/
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struct tegra_camera_dev_ops {
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int (*set_rate)(struct tegra_camera_dev_info *cdev_info, unsigned long rate);
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};
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/**
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* struct tegra_camera_dev_info - camera devices information
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* @priv: a unique identifier assigned during registration
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* @hw_type: type of HW engine as defined by the enum above
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* @bus_width: csi bus width for clock calculation
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* @overhead: hw/ sw overhead considered while calculations
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* @ppc: HW capability, pixels per clock
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* @bw: calculated bw for this node
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* @use_max: populated by hw engine to decide it's clocking policy
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* @memory_latency: latency allowed for memory freq scaling
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* @pdev: pointer to platform_data
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* @sensor_type: type of sensor as defined by the enum above
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* @pixel_rate: pixel rate coming out of the sensor
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* @pixel_bit_depth: bits per pixel
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* @bpp: bytes per pixel
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* @stream_on: stream enabled on the channel
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* @device_node: list node
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* @ops: operation callbacks of the camera device
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*/
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struct tegra_camera_dev_info {
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void *priv;
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u32 hw_type;
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u32 bus_width;
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u32 overhead;
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u64 lane_speed;
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u32 lane_num;
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u32 ppc;
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u64 pg_clk_rate;
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u64 bw;
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bool use_max;
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u32 memory_latency;
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struct platform_device *pdev;
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u32 sensor_type;
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u64 pixel_rate;
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u32 pixel_bit_depth;
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u32 bpp;
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bool stream_on;
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struct list_head device_node;
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const struct tegra_camera_dev_ops *ops;
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};
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int tegra_camera_update_isobw(void);
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int tegra_camera_device_register(struct tegra_camera_dev_info *cdev_info,
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void *priv);
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int tegra_camera_device_unregister(void *priv);
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int tegra_camera_get_device_list_entry(const u32 hw_type, const void *priv,
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struct tegra_camera_dev_info *cdev_info);
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int tegra_camera_get_device_list_stats(u32 *n_sensors, u32 *n_hwtypes);
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int tegra_camera_update_clknbw(void *priv, bool stream_on);
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#endif
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