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There are three clks for MGBE which needs to be set based on UPHY GBE mode and PHY line rate. o MGBE_MAC_DIV_CLK will be set based on PHY line rate o MGBE_MAC_TX/TX_PCS clks will be set based on UPHY GBE mode Below are the settings - UPHY GBE mode = 10G: =================== Possible MAC working rates: 10G/5G/2.5G 1) MAC DIVISOR: 312.5MHz, 312.5/2MHZ and 312.5/4MHz 2) TX CLK: 644.5MHZ 3) TX PCS_CLK: 156.5MHz UPHY GBE mode = 5G: ================== Possible MAC working rates: 5G/2.5G 1) MAC DIVISOR: 312.5/2MHz and 312.5/4MHz 2) TX CLK: 322.2MHZ 3) TX PCS_CLK: 78.125MHz Bug 200739493 Change-Id: Ie6b21f87d2077b8be621a32b2034b4eff1eb391e Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2541313 Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Narayan Reddy <narayanr@nvidia.com> GVS: Gerrit_Virtual_Submit