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92ac7bc35a
Port camera drivers below from /kenrel/nvidia to /kernel/nvidia-oot as OOT modules: - Fusa-capture driver - Tegra V4L2 framework driver - vi/csi driver - tegra camera platform driver Change-Id: I390af27096425bb11e0934201dd1a90f001bb3fa Signed-off-by: Frank Chen <frankc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2780698 Reviewed-by: FNU Raunak <fraunak@nvidia.com> Reviewed-by: Ankur Pawar <ankurp@nvidia.com> Reviewed-by: Shiva Dubey <sdubey@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* NVIDIA Tegra Video Input Device Driver Core Helpers
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*
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* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __TEGRA_CORE_H__
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#define __TEGRA_CORE_H__
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#include <media/v4l2-subdev.h>
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/* Minimum and maximum width and height common to Tegra video input device. */
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#define TEGRA_MIN_WIDTH 32U
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#define TEGRA_MAX_WIDTH 32768U
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#define TEGRA_MIN_HEIGHT 32U
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#define TEGRA_MAX_HEIGHT 32768U
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/* Width alignment */
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#define TEGRA_WIDTH_ALIGNMENT 1
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/* Stride alignment */
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#define TEGRA_STRIDE_ALIGNMENT 1
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/* Height alignment */
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#define TEGRA_HEIGHT_ALIGNMENT 1
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/* Size alignment */
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#define TEGRA_SIZE_ALIGNMENT 0
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/* 1080p resolution as default resolution for test pattern generator */
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#define TEGRA_DEF_WIDTH 1920
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#define TEGRA_DEF_HEIGHT 1080
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#define TEGRA_VF_DEF MEDIA_BUS_FMT_SRGGB10_1X10
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#define TEGRA_IMAGE_FORMAT_DEF 32
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enum tegra_image_dt {
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TEGRA_IMAGE_DT_YUV420_8 = 24,
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TEGRA_IMAGE_DT_YUV420_10,
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TEGRA_IMAGE_DT_YUV420CSPS_8 = 28,
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TEGRA_IMAGE_DT_YUV420CSPS_10,
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TEGRA_IMAGE_DT_YUV422_8,
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TEGRA_IMAGE_DT_YUV422_10,
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TEGRA_IMAGE_DT_RGB444,
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TEGRA_IMAGE_DT_RGB555,
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TEGRA_IMAGE_DT_RGB565,
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TEGRA_IMAGE_DT_RGB666,
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TEGRA_IMAGE_DT_RGB888,
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TEGRA_IMAGE_DT_RAW6 = 40,
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TEGRA_IMAGE_DT_RAW7,
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TEGRA_IMAGE_DT_RAW8,
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TEGRA_IMAGE_DT_RAW10,
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TEGRA_IMAGE_DT_RAW12,
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TEGRA_IMAGE_DT_RAW14,
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};
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/* Supported CSI to VI Data Formats */
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enum tegra_vf_code {
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TEGRA_VF_RAW6 = 0,
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TEGRA_VF_RAW7,
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TEGRA_VF_RAW8,
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TEGRA_VF_RAW10,
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TEGRA_VF_RAW12,
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TEGRA_VF_RAW14,
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TEGRA_VF_EMBEDDED8,
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TEGRA_VF_RGB565,
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TEGRA_VF_RGB555,
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TEGRA_VF_RGB888,
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TEGRA_VF_RGB444,
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TEGRA_VF_RGB666,
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TEGRA_VF_YUV422,
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TEGRA_VF_YUV420,
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TEGRA_VF_YUV420_CSPS,
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};
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/**
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* struct tegra_frac
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* @numerator: numerator of the fraction
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* @denominator: denominator of the fraction
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*/
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struct tegra_frac {
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unsigned int numerator;
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unsigned int denominator;
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};
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/**
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* struct tegra_video_format - Tegra video format description
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* @vf_code: video format code
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* @width: format width in bits per component
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* @code: media bus format code
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* @bpp: bytes per pixel fraction (when stored in memory)
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* @img_fmt: image format
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* @img_dt: image data type
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* @fourcc: V4L2 pixel format FCC identifier
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* @description: format description, suitable for userspace
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*/
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struct tegra_video_format {
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enum tegra_vf_code vf_code;
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unsigned int width;
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unsigned int code;
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struct tegra_frac bpp;
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u32 img_fmt;
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enum tegra_image_dt img_dt;
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u32 fourcc;
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__u8 description[32];
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};
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#define TEGRA_VIDEO_FORMAT(VF_CODE, BPP, MBUS_CODE, FRAC_BPP_NUM, \
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FRAC_BPP_DEN, FORMAT, DATA_TYPE, FOURCC, DESCRIPTION) \
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{ \
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TEGRA_VF_##VF_CODE, \
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BPP, \
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MEDIA_BUS_FMT_##MBUS_CODE, \
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{FRAC_BPP_NUM, FRAC_BPP_DEN}, \
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TEGRA_IMAGE_FORMAT_##FORMAT, \
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TEGRA_IMAGE_DT_##DATA_TYPE, \
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V4L2_PIX_FMT_##FOURCC, \
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DESCRIPTION, \
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}
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u32 tegra_core_get_word_count(unsigned int frame_width,
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const struct tegra_video_format *fmt);
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u32 tegra_core_bytes_per_line(unsigned int width, unsigned int align,
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const struct tegra_video_format *fmt);
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const struct tegra_video_format *tegra_core_get_default_format(void);
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#endif
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