mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 09:11:26 +03:00
7dd632ff96
- support Android-14 - support Linux kernel 6.9 - support 6G regulation - support Thermal protection - support TX shortcut to reduce CPU loading - fix some coverity issues - Use RTW regulatory version rtk_8852CE_M.2_2230-67-52 - default enable con-current and MCC Bug 4667769 Bug 4667981 Change-Id: Iee069ecdd1f00a0b78285d0a4ef5778ed9ace478 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3195601 Tested-by: Shobek Attupurath <sattupurath@nvidia.com> Reviewed-by: Revanth Kumar Uppala <ruppala@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
101 lines
3.9 KiB
C
101 lines
3.9 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _TEST_MODULE_H_
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#define _TEST_MODULE_H_
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#ifdef CONFIG_PHL_TEST_SUITE
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u8 phl_test_module_init(struct phl_info_t *phl_info);
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void phl_test_module_deinit(struct rtw_phl_com_t* phl_com);
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u8 phl_test_module_start(struct rtw_phl_com_t* phl_com);
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void phl_test_module_stop(struct rtw_phl_com_t* phl_com);
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#else
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#define phl_test_module_init(phl_info) true
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#define phl_test_module_deinit(phl_com)
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#define phl_test_module_start(phl_com) true
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#define phl_test_module_stop(phl_com)
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#endif /*CONFIG_PHL_TEST_SUITE*/
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#ifdef CONFIG_PHL_TEST_MP
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/* phl test mp command */
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enum rtw_phl_status phl_test_mp_alloc(struct phl_info_t *phl_info, void *hal, void **mp);
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void phl_test_mp_free(void **mp);
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void phl_test_mp_init(void *mp);
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void phl_test_mp_deinit(void *mp);
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void phl_test_mp_start(void *mp, u8 tm_mode);
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void phl_test_mp_stop(void *mp, u8 tm_mode);
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void phl_test_mp_cmd_process(void *mp, void *buf, u32 buf_len, u8 submdid);
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void phl_test_mp_get_rpt(void *mp, void *buf, u32 buf_len);
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#else
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/* phl test mp command */
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#define phl_test_mp_alloc(phl_info, hal, mp) RTW_PHL_STATUS_SUCCESS
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#define phl_test_mp_free(mp)
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#define phl_test_mp_init(mp)
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#define phl_test_mp_deinit(mp)
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#define phl_test_mp_start(mp, tm_mode)
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#define phl_test_mp_stop(mp, tm_mode)
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#define phl_test_mp_cmd_process(mp, buf, buf_len, submdid)
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#define phl_test_mp_get_rpt(mp, buf, buf_len)
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#endif /* CONFIG_PHL_TEST_MP */
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#ifdef CONFIG_PHL_TEST_VERIFY
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/* phl test verify command */
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enum rtw_phl_status phl_test_verify_alloc(struct phl_info_t *phl_info, void *hal, void **ctx);
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void phl_test_verify_free(void **ctx);
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void phl_test_verify_init(void *ctx);
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void phl_test_verify_deinit(void *ctx);
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void phl_test_verify_start(void *ctx);
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void phl_test_verify_stop(void *ctx);
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void phl_test_verify_cmd_process(void *ctx, void *buf, u32 buf_len, u8 submdid);
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void phl_test_verify_get_rpt(void *ctx, void *buf, u32 buf_len);
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#else
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/* phl test verify command */
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#define phl_test_verify_alloc(phl_info, hal, ctx) RTW_PHL_STATUS_SUCCESS
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#define phl_test_verify_free(ctx)
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#define phl_test_verify_init(ctx)
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#define phl_test_verify_deinit(ctx)
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#define phl_test_verify_start(ctx)
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#define phl_test_verify_stop(ctx)
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#define phl_test_verify_cmd_process(ctx, buf, buf_len, submdid)
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#define phl_test_verify_get_rpt(ctx, buf, buf_len)
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#endif /* CONFIG_PHL_TEST_VERIFY */
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#ifdef CONFIG_PHL_TEST_FPGA
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/* phl test fpga command */
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enum rtw_phl_status phl_test_fpga_alloc(struct phl_info_t *phl_info, void *hal, void **fpga);
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void phl_test_fpga_free(void **fpga);
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void phl_test_fpga_init(void *fpga);
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void phl_test_fpga_deinit(void *fpga);
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void phl_test_fpga_start(void *fpga, u8 tm_mode);
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void phl_test_fpga_stop(void *fpga, u8 tm_mode);
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void phl_test_fpga_cmd_process(void *fpga, void *buf, u32 buf_len, u8 submdid);
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void phl_test_fpga_get_rpt(void *fpga, void *buf, u32 buf_len);
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#else
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/* phl test fpga command */
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#define phl_test_fpga_alloc(phl_info, hal, fpga) RTW_PHL_STATUS_SUCCESS
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#define phl_test_fpga_free(fpga)
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#define phl_test_fpga_init(fpga)
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#define phl_test_fpga_deinit(fpga)
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#define phl_test_fpga_start(fpga, tm_mode)
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#define phl_test_fpga_stop(fpga, tm_mode)
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#define phl_test_fpga_cmd_process(fpga, buf, buf_len, submdid)
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#define phl_test_fpga_get_rpt(fpga, buf, buf_len)
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#endif /* CONFIG_PHL_TEST_FPGA */
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#endif /* _TEST_MODULE_H_ */
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