mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 09:11:26 +03:00
9d520f3d07
There was a plan to deprecate master volume control since it was thought that per channel control will be sufficient and master volume application can be emulated in user space by programming same volume to all channels. But this means we would not really use a HW feature which has a provision to automatically apply CH0 volume settings to all remaining channels. HW has a per channel control bit, based on which it decides to apply a channel specific setting or a common setting across all channels. Driver has both master volume and per channel volume mixer controls. Based on the control user updates, enable or disable the per channel control. Use below scheme for volume updates: * If master volume mixer control is updated, disable per channel control and only CH0 volume register is programmed. SW can store same volume across all channels. * If a channel specific control is updated, enable per channel control and program specific channel volume register. Above applies to mute/unmute functions as well and thus corresponding control blocks are similarly updated. The volume settings are stored in SW and the same is used for the user space queries via mixer controls. But mute settings are not stored in SW and are always directly read from HW since it belongs to a volatile register. The mute control read function is modified to return proper settings when queried from user space. Bug 200766084 Change-Id: Iad8b5c09c424731e841863bfd5ce32d07ff9e684 Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.10/+/2599601 Reviewed-by: Sheetal . <sheetal@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Asha Talambedu <atalambedu@nvidia.com> Reviewed-by: Mohan Kumar D <mkumard@nvidia.com> Reviewed-by: Sharad Gupta <sharadg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
125 lines
4.2 KiB
C
125 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* tegra210_mvc.h - Definitions for Tegra210 MVC driver
|
|
*
|
|
* Copyright (c) 2014-2021 NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
*/
|
|
|
|
#ifndef __TEGRA210_MVC_H__
|
|
#define __TEGRA210_MVC_H__
|
|
|
|
/*
|
|
* MVC_RX registers are with respect to AXBAR.
|
|
* The data is coming from AXBAR to MVC for playback.
|
|
*/
|
|
#define TEGRA210_MVC_RX_STATUS 0x0c
|
|
#define TEGRA210_MVC_RX_INT_STATUS 0x10
|
|
#define TEGRA210_MVC_RX_INT_MASK 0x14
|
|
#define TEGRA210_MVC_RX_INT_SET 0x18
|
|
#define TEGRA210_MVC_RX_INT_CLEAR 0x1c
|
|
#define TEGRA210_MVC_RX_CIF_CTRL 0x20
|
|
#define TEGRA210_MVC_RX_CYA 0x24
|
|
#define TEGRA210_MVC_RX_DBG 0x28
|
|
|
|
/*
|
|
* MVC_TX registers are with respect to AXBAR.
|
|
* The data is going out of MVC for playback.
|
|
*/
|
|
#define TEGRA210_MVC_TX_STATUS 0x4c
|
|
#define TEGRA210_MVC_TX_INT_STATUS 0x50
|
|
#define TEGRA210_MVC_TX_INT_MASK 0x54
|
|
#define TEGRA210_MVC_TX_INT_SET 0x58
|
|
#define TEGRA210_MVC_TX_INT_CLEAR 0x5c
|
|
#define TEGRA210_MVC_TX_CIF_CTRL 0x60
|
|
#define TEGRA210_MVC_TX_CYA 0x64
|
|
#define TEGRA210_MVC_TX_DBG 0x68
|
|
|
|
/* Register offsets from TEGRA210_MVC*_BASE */
|
|
#define TEGRA210_MVC_ENABLE 0x80
|
|
#define TEGRA210_MVC_SOFT_RESET 0x84
|
|
#define TEGRA210_MVC_CG 0x88
|
|
#define TEGRA210_MVC_STATUS 0x90
|
|
#define TEGRA210_MVC_INT_STATUS 0x94
|
|
#define TEGRA210_MVC_CTRL 0xa8
|
|
#define TEGRA210_MVC_SWITCH 0xac
|
|
#define TEGRA210_MVC_INIT_VOL 0xb0
|
|
#define TEGRA210_MVC_TARGET_VOL 0xd0
|
|
#define TEGRA210_MVC_DURATION 0xf0
|
|
#define TEGRA210_MVC_DURATION_INV 0xf4
|
|
#define TEGRA210_MVC_POLY_N1 0xf8
|
|
#define TEGRA210_MVC_POLY_N2 0xfc
|
|
#define TEGRA210_MVC_PEAK_CTRL 0x100
|
|
#define TEGRA210_MVC_CFG_RAM_CTRL 0x104
|
|
#define TEGRA210_MVC_CFG_RAM_DATA 0x108
|
|
#define TEGRA210_MVC_PEAK_VALUE 0x10c
|
|
#define TEGRA210_MVC_CONFIG_ERR_TYPE 0x12c
|
|
#define TEGRA210_MVC_CYA 0x130
|
|
#define TEGRA210_MVC_DBG 0x138
|
|
|
|
/* Fields in TEGRA210_MVC_ENABLE */
|
|
#define TEGRA210_MVC_EN_SHIFT 0
|
|
#define TEGRA210_MVC_EN (1 << TEGRA210_MVC_EN_SHIFT)
|
|
|
|
#define TEGRA210_MVC_MUTE_SHIFT 8
|
|
#define TEGRA210_MUTE_MASK_EN 0xff
|
|
#define TEGRA210_MVC_MUTE_MASK (TEGRA210_MUTE_MASK_EN << TEGRA210_MVC_MUTE_SHIFT)
|
|
#define TEGRA210_MVC_MUTE_EN (TEGRA210_MUTE_MASK_EN << TEGRA210_MVC_MUTE_SHIFT)
|
|
#define TEGRA210_MVC_CH0_MUTE_EN 1
|
|
#define TEGRA210_MVC_CH0_MUTE_MASK (TEGRA210_MVC_CH0_MUTE_EN << TEGRA210_MVC_MUTE_SHIFT)
|
|
|
|
#define TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT 30
|
|
#define TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK (1 << TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT)
|
|
#define TEGRA210_MVC_PER_CHAN_CTRL_EN (1 << TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT)
|
|
|
|
#define TEGRA210_MVC_CURVE_TYPE_SHIFT 1
|
|
#define TEGRA210_MVC_CURVE_TYPE_MASK (1 << TEGRA210_MVC_CURVE_TYPE_SHIFT)
|
|
|
|
#define TEGRA210_MVC_VOLUME_SWITCH_SHIFT 2
|
|
#define TEGRA210_MVC_VOLUME_SWITCH_MASK (1 << TEGRA210_MVC_VOLUME_SWITCH_SHIFT)
|
|
#define TEGRA210_MVC_VOLUME_SWITCH_TRIGGER (1 << TEGRA210_MVC_VOLUME_SWITCH_SHIFT)
|
|
#define TEGRA210_MVC_CTRL_DEFAULT 0x40000003
|
|
|
|
#define TEGRA210_MVC_INIT_VOL_DEFAULT_POLY 0x01000000
|
|
#define TEGRA210_MVC_INIT_VOL_DEFAULT_LINEAR 0x00000000
|
|
|
|
#define TEGRA210_MVC_BYPASS_MODE_SHIFT 31
|
|
#define TEGRA210_MVC_BYPASS_MODE_MASK (1 << TEGRA210_MVC_BYPASS_MODE_SHIFT)
|
|
|
|
/* Fields in TEGRA210_MVC ram ctrl */
|
|
#define TEGRA210_MVC_CFG_RAM_CTRL_RW_SHIFT 14
|
|
#define TEGRA210_MVC_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_MVC_CFG_RAM_CTRL_RW_SHIFT)
|
|
|
|
#define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13
|
|
#define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT)
|
|
|
|
#define TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12
|
|
#define TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)
|
|
|
|
#define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_SHIFT 0
|
|
#define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_MASK (0x1ff << TEGRA210_MVC_CFG_RAM_CTRL_ADDR_SHIFT)
|
|
|
|
#define REG_SIZE 4
|
|
#define TEGRA210_MVC_MAX_CHAN_COUNT 8
|
|
#define TEGRA210_MVC_REG_OFFSET(reg, i) (reg + (REG_SIZE * i))
|
|
|
|
enum {
|
|
CURVE_POLY,
|
|
CURVE_LINEAR,
|
|
};
|
|
|
|
struct tegra210_mvc {
|
|
struct regmap *regmap;
|
|
int poly_coeff[9];
|
|
int poly_n1, poly_n2, duration, duration_inv;
|
|
int volume[TEGRA210_MVC_MAX_CHAN_COUNT];
|
|
unsigned int curve_type;
|
|
unsigned int ctrl_value;
|
|
unsigned int cif_channels;
|
|
unsigned int audio_bits;
|
|
unsigned int format_in;
|
|
bool bypass_mode;
|
|
};
|
|
|
|
#endif
|