Sameer Pujar 5c3be8602c ASoC: tegra-alt: expose i2s fifo threshold control ...

For some of the use cases we might require to program the fifo
thresholds of Rx cif. Until now we have been using fixed
values for Rx cif. This patch exports the configurability
option to the user space. If no threshold value is specified,
it uses the fixed values as per the previous state of the driver.
Threshold needs to be programmed in terms of frames, where
1 frame = no. of channels * 1 word.

Note: The same control for Tx cif is not needed as this register
is RO and not allowed to be programmed. Reset value is used for
Tx cif.

Bug 200283222

Change-Id: If1e5379dd874a0f1f6f1d9ae71465ac8c1f9f071
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-on: http://git-master/r/1319742
Reviewed-by: Mohan Kumar D <mkumard@nvidia.com>
Reviewed-by: Dipesh Gandhi <dipeshg@nvidia.com>
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
GVS: Gerrit_Virtual_Submit

2022-09-29 15:30:21 +05:30

..

soc

ASoC: tegra-alt: expose i2s fifo threshold control

2022-09-29 15:30:21 +05:30