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For T23x, we have a separate R5 based cluster named as Display Controller Engine(DCE) to run our Display RM code. This driver will run on CPU with the following functionality: Via debugfs for test and bring-up purposes: 1. Reads the DCE firmware image into DRAM. 2. Sets up DCE AST to cover the DCE firmware image. 3. Sets up R5 reset vector to point to DCE firmware entry point 4. Brings DCE out of reset 5. Dumps various regsiters for debug In production env: 1. Manages interrupts to CPU from DCE 2. Uses bootstrap command interface to define Admin IPC 3. Locks down bootstrap command interface 4. Uses Admin IPC to define message IPC 5. Uses Admin IPC to define message IPC payload area 6. Uses Admin IPC to set IPC channels 6. Uses Admin IPC to define crashdump area (optional) 7. Provides IPC interfaces for any DCE Client running on CCPLEX including Display RM. 8. Uses Admin IPC to set logging level (optional) This patch puts a framework in place with the following features : 1. Firmware Loading 2. AST Configuration 3. DCE Reset with EVP Programming 4. Logging Infra 5. Debugfs Support 6. Interrupt Handling 7. Mailbox Programming 8. IPC Programming 9. DCE Client Interface 10. Ftrace Support for debug purposes Change-Id: Idd28cd9254706c7313f531fcadaa7024a5b344e7 Signed-off-by: Arun Swain <arswain@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2289865 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-by: Santosh Galma <galmar@nvidia.com> Reviewed-by: Mitch Luban <mluban@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Mahesh Kumar <mahkumar@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
245 lines
5.6 KiB
C
245 lines
5.6 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <dce.h>
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#include <dce-log.h>
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#include <dce-util-common.h>
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#define DCE_MAX_NO_SMB 8
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#define DCE_MAX_HSP_IE 8
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/**
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* smb_regs is a 1D array of read-only pointers to a function returning u32.
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*
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* Array of functions that retrun base addresses of shared maiboxes registers
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* in DCE cluster based on the mailbox id.
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*/
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static u32 (*const smb_regs[DCE_MAX_NO_SMB])(void) = {
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hsp_sm0_r,
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hsp_sm1_r,
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hsp_sm2_r,
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hsp_sm3_r,
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hsp_sm4_r,
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hsp_sm5_r,
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hsp_sm6_r,
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hsp_sm7_r,
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};
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/**
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* smb_full_ie_regs is a 1D array of read-only pointers to a function
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* returning u32.
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*
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* Array of functions that retrun base addresses of full IE for shared
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* maiboxes registers in DCE cluster based on the mailbox id.
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*/
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static u32 (*const smb_full_ie_regs[DCE_MAX_NO_SMB])(void) = {
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hsp_sm0_full_int_ie_r,
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hsp_sm1_full_int_ie_r,
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hsp_sm2_full_int_ie_r,
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hsp_sm3_full_int_ie_r,
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hsp_sm4_full_int_ie_r,
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hsp_sm5_full_int_ie_r,
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hsp_sm6_full_int_ie_r,
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hsp_sm7_full_int_ie_r,
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};
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/**
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* smb_empty_ie_regs is a 1D array of read-only pointers to a function
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* returning u32.
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*
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* Array of functions that retrun base addresses of empty IE for shared
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* maiboxes registers in DCE cluster based on the mailbox id.
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*/
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static u32 (*const smb_empty_ie_regs[DCE_MAX_NO_SMB])(void) = {
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hsp_sm0_empty_int_ie_r,
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hsp_sm1_empty_int_ie_r,
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hsp_sm2_empty_int_ie_r,
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hsp_sm3_empty_int_ie_r,
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hsp_sm4_empty_int_ie_r,
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hsp_sm5_empty_int_ie_r,
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hsp_sm6_empty_int_ie_r,
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hsp_sm7_empty_int_ie_r,
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};
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/**
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* dce_smb_set - Set an u32 value to smb_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @val : val to set.
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* @id : Shared Mailbox Id.
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*
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* Return : Void
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*/
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void dce_smb_set(struct tegra_dce *d, u32 val, u8 id)
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{
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if (id >= DCE_MAX_NO_SMB) {
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dce_err(d, "Invalid Shared Mailbox ID");
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return;
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}
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dce_writel(d, smb_regs[id](), val);
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}
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/**
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* dce_smb_set_full_ie - Set an u32 value to smb_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @en : enable if true and disable if false
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* @id : Shared Mailbox Id.
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*
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* Return : Void
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*/
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void dce_smb_set_full_ie(struct tegra_dce *d, bool en, u8 id)
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{
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u32 val = en ? 1U : 0U;
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if (id >= DCE_MAX_NO_SMB) {
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dce_err(d, "Invalid Shared Mailbox ID");
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return;
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}
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dce_writel(d, smb_full_ie_regs[id](), val);
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}
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/**
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* dce_smb_read_full_ie - Set an u32 value to smb_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @id : Shared Mailbox Id.
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*
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* Return : u32 register value
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*/
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u32 dce_smb_read_full_ie(struct tegra_dce *d, u8 id)
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{
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if (id >= DCE_MAX_NO_SMB) {
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dce_err(d, "Invalid Shared Mailbox ID");
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return 0xffffffff; /* TODO : Add DCE Error Numbers */
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}
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return dce_readl(d, smb_full_ie_regs[id]());
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}
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/**
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* dce_smb_enable_empty_ie - Set an u32 value to smb_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @en : enable if true and disable if false
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* @id : Shared Mailbox Id.
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*
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* Return : Void
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*/
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void dce_smb_set_empty_ie(struct tegra_dce *d, bool en, u8 id)
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{
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u32 val = en ? 1U : 0U;
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if (id >= DCE_MAX_NO_SMB) {
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dce_err(d, "Invalid Shared Mailbox ID");
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return;
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}
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dce_writel(d, smb_empty_ie_regs[id](), val);
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}
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/**
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* dce_smb_read - Read the u32 value from smb_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @id : Shared Mailbox Id.
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*
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* Return : actual value if successful, 0xffffffff for errors scenarios
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*/
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u32 dce_smb_read(struct tegra_dce *d, u8 id)
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{
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if (id >= DCE_MAX_NO_SMB) {
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dce_err(d, "Invalid Shared Mailbox ID : %x", id);
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return 0xffffffff; /* TODO : Add DCE Error Numbers */
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}
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return dce_readl(d, smb_regs[id]());
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}
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/**
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* hsp_int_ie_regs is a 1D array of read-only pointers to a
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* function returning u32.
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*
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* Array of functions that retrun base addresses of hsp IE
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* regs in DCE cluster based on the id.
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*/
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static u32 (*const hsp_int_ie_regs[DCE_MAX_HSP_IE])(void) = {
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hsp_int_ie0_r,
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hsp_int_ie1_r,
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hsp_int_ie2_r,
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hsp_int_ie3_r,
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hsp_int_ie4_r,
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hsp_int_ie5_r,
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hsp_int_ie6_r,
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hsp_int_ie7_r,
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};
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/**
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* dce_hsp_ie_read - Read the u32 value from hsp_int_ie#n
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* in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @id : Shared IE Id.
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*
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* Return : actual value if successful, 0xffffffff for errors scenarios
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*/
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u32 dce_hsp_ie_read(struct tegra_dce *d, u8 id)
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{
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if (id >= DCE_MAX_HSP_IE) {
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dce_err(d, "Invalid Shared HSP IE ID");
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return 0xffffffff; /* TODO : Add DCE Error Numbers */
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}
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return dce_readl(d, hsp_int_ie_regs[id]());
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}
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/**
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* dce_hsp_ie_write - Read the u32 value from hsp_int_ie#n
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* in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @val : Value to be written
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* @id : Shared IE Id.
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*
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* Return : void
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*/
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void dce_hsp_ie_write(struct tegra_dce *d, u32 val, u8 id)
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{
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if (id >= DCE_MAX_HSP_IE) {
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dce_err(d, "Invalid Shared HSP IE ID");
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return;
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}
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dce_writel(d, hsp_int_ie_regs[id](),
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val | dce_readl(d, hsp_int_ie_regs[id]()));
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}
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/**
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* dce_hsp_ir_read - Read the u32 value from hsp_int_ir
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* in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : actual value if successful, 0xffffffff for errors scenarios
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*/
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u32 dce_hsp_ir_read(struct tegra_dce *d)
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{
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return dce_readl(d, hsp_int_ir_r());
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}
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