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606f03fbf2
For T23x, we have a separate R5 based cluster named as Display Controller Engine(DCE) to run our Display RM code. This driver will run on CPU with the following functionality: Via debugfs for test and bring-up purposes: 1. Reads the DCE firmware image into DRAM. 2. Sets up DCE AST to cover the DCE firmware image. 3. Sets up R5 reset vector to point to DCE firmware entry point 4. Brings DCE out of reset 5. Dumps various regsiters for debug In production env: 1. Manages interrupts to CPU from DCE 2. Uses bootstrap command interface to define Admin IPC 3. Locks down bootstrap command interface 4. Uses Admin IPC to define message IPC 5. Uses Admin IPC to define message IPC payload area 6. Uses Admin IPC to set IPC channels 6. Uses Admin IPC to define crashdump area (optional) 7. Provides IPC interfaces for any DCE Client running on CCPLEX including Display RM. 8. Uses Admin IPC to set logging level (optional) This patch puts a framework in place with the following features : 1. Firmware Loading 2. AST Configuration 3. DCE Reset with EVP Programming 4. Logging Infra 5. Debugfs Support 6. Interrupt Handling 7. Mailbox Programming 8. IPC Programming 9. DCE Client Interface 10. Ftrace Support for debug purposes Change-Id: Idd28cd9254706c7313f531fcadaa7024a5b344e7 Signed-off-by: Arun Swain <arswain@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2289865 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-by: Santosh Galma <galmar@nvidia.com> Reviewed-by: Mitch Luban <mluban@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Mahesh Kumar <mahkumar@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
145 lines
3.2 KiB
C
145 lines
3.2 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <dce.h>
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#include <dce-log.h>
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#include <dce-util-common.h>
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#define DCE_MAX_NO_SS 4
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/**
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* ss_set_regs is a 1D array of read-only pointers to a function returning u32.
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*
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* Array of functions that retrun base addresses of shared semaphores set
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* registers in DCE cluster based on the semaphore id.
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*/
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static u32 (*const ss_set_regs[DCE_MAX_NO_SS])(void) = {
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hsp_ss0_set_r,
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hsp_ss1_set_r,
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hsp_ss2_set_r,
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hsp_ss3_set_r,
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};
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/**
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* ss_clear_regs is a 1D array of read-only pointers to a function
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* returning u32.
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*
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* Array of functions that retrun base addresses of shared semaphores clear
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* registers in DCE cluster based on the semaphore id.
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*/
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static u32 (*const ss_clear_regs[DCE_MAX_NO_SS])(void) = {
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hsp_ss0_clr_r,
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hsp_ss1_clr_r,
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hsp_ss2_clr_r,
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hsp_ss3_clr_r,
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};
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/**
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* ss_state_regs is a 1D array of read-only pointers to a function
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* returning u32.
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*
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* Array of functions that retrun base addresses of shared semaphores state
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* registers in DCE cluster based on the semaphore id.
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*/
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static u32 (*const ss_state_regs[DCE_MAX_NO_SS])(void) = {
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hsp_ss0_state_r,
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hsp_ss1_state_r,
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hsp_ss2_state_r,
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hsp_ss3_state_r,
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};
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/**
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* dce_ss_get_state - Get the state of ss_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @id : Shared Semaphore Id.
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*
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* Return : u32
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*/
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u32 dce_ss_get_state(struct tegra_dce *d, u8 id)
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{
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return dce_readl(d, ss_state_regs[id]());
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}
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/**
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* dce_ss_set - Set an u32 value to ss_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @bpos : bit to be set.
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* @id : Shared Semaphore Id.
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*
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* Return : Void
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*/
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void dce_ss_set(struct tegra_dce *d, u8 bpos, u8 id)
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{
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unsigned long val = 0U;
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if (id >= DCE_MAX_NO_SS) {
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dce_err(d, "Invalid Shared Semaphore ID");
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return;
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}
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val = dce_ss_get_state(d, id);
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/**
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* Debug info. please remove
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*/
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dce_info(d, "Current Value in SS#%d : %lx", id, val);
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/**
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* TODO :Use DCE_INSERT here.
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*/
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dce_bitmap_set(&val, bpos, 1);
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/**
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* Debug info. please remove
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*/
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dce_info(d, "Value after bitmap operation : %lx", val);
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dce_writel(d, ss_set_regs[id](), (u32)val);
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/**
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* Debug info. please remove
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*/
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val = dce_ss_get_state(d, id);
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dce_info(d, "Current Value in SS#%d : %lx", id, val);
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}
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/**
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* dce_ss_clear - Clear a bit in ss_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @bpos : bit to be cleared.
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* @id : Shared Semaphore Id.
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*
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* Return : Void
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*/
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void dce_ss_clear(struct tegra_dce *d, u8 bpos, u8 id)
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{
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unsigned long val;
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if (id >= DCE_MAX_NO_SS) {
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dce_err(d, "Invalid Shared Semaphore ID");
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return;
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}
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val = dce_ss_get_state(d, id);
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dce_bitmap_set(&val, bpos, 1);
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dce_writel(d, ss_set_regs[id](), val);
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}
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