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606f03fbf2
For T23x, we have a separate R5 based cluster named as Display Controller Engine(DCE) to run our Display RM code. This driver will run on CPU with the following functionality: Via debugfs for test and bring-up purposes: 1. Reads the DCE firmware image into DRAM. 2. Sets up DCE AST to cover the DCE firmware image. 3. Sets up R5 reset vector to point to DCE firmware entry point 4. Brings DCE out of reset 5. Dumps various regsiters for debug In production env: 1. Manages interrupts to CPU from DCE 2. Uses bootstrap command interface to define Admin IPC 3. Locks down bootstrap command interface 4. Uses Admin IPC to define message IPC 5. Uses Admin IPC to define message IPC payload area 6. Uses Admin IPC to set IPC channels 6. Uses Admin IPC to define crashdump area (optional) 7. Provides IPC interfaces for any DCE Client running on CCPLEX including Display RM. 8. Uses Admin IPC to set logging level (optional) This patch puts a framework in place with the following features : 1. Firmware Loading 2. AST Configuration 3. DCE Reset with EVP Programming 4. Logging Infra 5. Debugfs Support 6. Interrupt Handling 7. Mailbox Programming 8. IPC Programming 9. DCE Client Interface 10. Ftrace Support for debug purposes Change-Id: Idd28cd9254706c7313f531fcadaa7024a5b344e7 Signed-off-by: Arun Swain <arswain@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2289865 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-by: Santosh Galma <galmar@nvidia.com> Reviewed-by: Mitch Luban <mluban@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Mahesh Kumar <mahkumar@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
112 lines
4.0 KiB
C
112 lines
4.0 KiB
C
/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* NVIDIA Corporation and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA Corporation is strictly prohibited.
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*/
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#ifndef DCE_BOOT_CMDS_H
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#define DCE_BOOT_CMDS_H
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#include <interface/dce-bitops.h>
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/*
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* Version of the bootstrap command interface.
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*
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* This MUST be updated any time any changes are made to the
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* bootstrap commands.
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*
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* To keep things simple, this value should be incremented by 1
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* each time changes are made.
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*/
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#define DCE_BOOT_CMD_VERSION_NUM 2
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/*
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* Defines the various bootstrap commands to DCE.
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*
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* These commands are relatively simple and are mainly used to
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* communicate with DCE during initialization.
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*
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* The fundamental layout of a command is:
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* Bit(s) Field Description
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* 31:31 GO Signals to the DCE that a command is to be
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* processed
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* 30:27 COMMAND Identifies the command that the DCE is to
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* process
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* 26 RESERVED should be 0
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* 25 HILO 0 = PARM is 19:0 of address
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* 1 = PARM is 39:20 of address
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* 24 RDWR 0 = read header
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* 1 = write header
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* 23:20 RESERVED should be 0
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* 19:0 PARM Parameter to the command
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*
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* Once the command has been processed and the CCPLEX receives an interrupt
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* from DCE, the mailbox used will contain any information about the result
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* of the command.
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*
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* The commands are:
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*
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* DCE_BOOT_CMD_VERSION returns the version of the interface
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* DCE_BOOT_CMD_SET_SID sets the SID for a buffer
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* DCE_BOOT_CMD_CHANNEL_INIT initialize an IVC channel
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* DCE_BOOT_CMD_SET_ADDR set the channel address
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* DCE_BOOT_CMD_GET_FSIZE get the size of the frame
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* DCE_BOOT_CMD_SET_NFRAMES set the number of frames
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* DCE_BOOT_CMD_RESET causes DCE to reset to its initial state.
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* This does not cause DCE to reboot. It mearly
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* indicates that all of memory buffers for IPC
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* will be ignored and the CCPLEX will have to
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* re-establish the memory again.
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*
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* DCE_BOOT_CMD_LOCK locks the admin command interface. Requires
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* a full reset of DCE to unlock.
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*/
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#define DCE_BOOT_CMD_GO DCE_BIT(31)
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#define DCE_BOOT_CMD_SET(_x_, _v_) DCE_INSERT(_x_, 30, 27, _v_)
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#define DCE_BOOT_CMD_GET(_x_) DCE_EXTRACT(_x_, 30, 27, uint32_t)
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#define DCE_BOOT_CMD_SET_HILO(_x_, _v_) DCE_INSERT(_x_, 25, 25, _v_)
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#define DCE_BOOT_CMD_GET_HILO(_x_) DCE_EXTRACT(_x_, 25, 25, uint32_t)
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#define DCE_BOOT_CMD_SET_RDWR(_x_, _v_) DCE_INSERT(_x_, 24, 24, _v_)
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#define DCE_BOOT_CMD_GET_RDWR(_x_) DCE_EXTRACT(_x_, 24, 24, uint32_t)
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#define DCE_BOOT_CMD_PARM_SET(_x_, _v_) DCE_INSERT(_x_, 19, 0, _v_)
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#define DCE_BOOT_CMD_PARM_GET(_x_) DCE_EXTRACT(_x_, 19, 0, uint32_t)
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/*
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* Commands
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*/
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#define DCE_BOOT_CMD_VERSION (0x00U)
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#define DCE_BOOT_CMD_SET_SID (0x01U)
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#define DCE_BOOT_CMD_CHANNEL_INIT (0x02U)
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#define DCE_BOOT_CMD_SET_ADDR (0x03U)
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#define DCE_BOOT_CMD_GET_FSIZE (0x04U)
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#define DCE_BOOT_CMD_SET_NFRAMES (0x05U)
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#define DCE_BOOT_CMD_RESET (0x06U)
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#define DCE_BOOT_CMD_LOCK (0x07U)
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#define DCE_BOOT_CMD_SET_AST_LENGTH (0x08U)
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#define DCE_BOOT_CMD_SET_AST_IOVA (0x09U)
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#define DCE_BOOT_CMD_SET_FSIZE (0x0AU)
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#define DCE_BOOT_CMD_UNUSED_11 (0x0BU)
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#define DCE_BOOT_CMD_UNUSED_12 (0x0CU)
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#define DCE_BOOT_CMD_UNUSED_13 (0x0DU)
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#define DCE_BOOT_CMD_UNUSED_14 (0x0EU)
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#define DCE_BOOT_CMD_UNUSED_15 (0x0FU)
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#define DCE_BOOT_CMD_NEXT (0x10U)
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/*
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* Boot Command Errors
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*/
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#define DCE_BOOT_CMD_ERR_FLAG DCE_BIT(23)
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#define DCE_BOOT_CMD_NO_ERROR 0U
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#define DCE_BOOT_CMD_ERR_BAD_COMMAND (1U | DCE_BOOT_CMD_ERR_FLAG)
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#define DCE_BOOT_CMD_ERR_UNIMPLEMENTED (2U | DCE_BOOT_CMD_ERR_FLAG)
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#define DCE_BOOT_CMD_ERR_IPC_SETUP (3U | DCE_BOOT_CMD_ERR_FLAG)
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#define DCE_BOOT_CMD_ERR_INVALID_NFRAMES (4U | DCE_BOOT_CMD_ERR_FLAG)
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#define DCE_BOOT_CMD_ERR_IPC_CREATE (5U | DCE_BOOT_CMD_ERR_FLAG)
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#define DCE_BOOT_CMD_ERR_LOCKED (6U | DCE_BOOT_CMD_ERR_FLAG)
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#endif
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