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606f03fbf2
For T23x, we have a separate R5 based cluster named as Display Controller Engine(DCE) to run our Display RM code. This driver will run on CPU with the following functionality: Via debugfs for test and bring-up purposes: 1. Reads the DCE firmware image into DRAM. 2. Sets up DCE AST to cover the DCE firmware image. 3. Sets up R5 reset vector to point to DCE firmware entry point 4. Brings DCE out of reset 5. Dumps various regsiters for debug In production env: 1. Manages interrupts to CPU from DCE 2. Uses bootstrap command interface to define Admin IPC 3. Locks down bootstrap command interface 4. Uses Admin IPC to define message IPC 5. Uses Admin IPC to define message IPC payload area 6. Uses Admin IPC to set IPC channels 6. Uses Admin IPC to define crashdump area (optional) 7. Provides IPC interfaces for any DCE Client running on CCPLEX including Display RM. 8. Uses Admin IPC to set logging level (optional) This patch puts a framework in place with the following features : 1. Firmware Loading 2. AST Configuration 3. DCE Reset with EVP Programming 4. Logging Infra 5. Debugfs Support 6. Interrupt Handling 7. Mailbox Programming 8. IPC Programming 9. DCE Client Interface 10. Ftrace Support for debug purposes Change-Id: Idd28cd9254706c7313f531fcadaa7024a5b344e7 Signed-off-by: Arun Swain <arswain@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2289865 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-by: Santosh Galma <galmar@nvidia.com> Reviewed-by: Mitch Luban <mluban@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Mahesh Kumar <mahkumar@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
37 lines
1.2 KiB
C
37 lines
1.2 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* NVIDIA Corporation and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA Corporation is strictly prohibited.
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*/
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#ifndef DCE_IPC_STATE_H
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#define DCE_IPC_STATE_H
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#include <interface/dce-bitops.h>
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/*
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* Flags used to denote the state of IPC data structures
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*/
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typedef uint32_t dce_ipc_flags_t;
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#define DCE_IPC_FL_VALID ((dce_ipc_flags_t)DCE_BIT(0))
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#define DCE_IPC_FL_REGISTERED ((dce_ipc_flags_t)DCE_BIT(1))
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#define DCE_IPC_FL_INIT ((dce_ipc_flags_t)DCE_BIT(2))
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#define DCE_IPC_FL_READY ((dce_ipc_flags_t)DCE_BIT(3))
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#define DCE_IPC_FL_RM_ALLOWED ((dce_ipc_flags_t)DCE_BIT(4))
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#define DCE_IPC_FL_MSG_HEADER ((dce_ipc_flags_t)DCE_BIT(15))
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/*
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* Different types of signal mechanisms
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*/
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typedef uint32_t dce_ipc_signal_type_t;
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#define DCE_IPC_SIGNAL_MAILBOX ((dce_ipc_signal_type_t)0U)
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#define DCE_IPC_SIGNAL_DOORBELL ((dce_ipc_signal_type_t)1U)
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#endif
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