mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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64b01b7616
- Added function definitions to control AON from kernel on T264. - Copy files dev-t264-aon.c and dev-t264-aon.h to drivers/platform/tegra/nvadsp/ - Patch chip_data,compatible and hdrs to dev.c for T264 AON Bug 4165898 Change-Id: Iad31d89a7bff722fed47f4c28b0b7193c13ce414 Signed-off-by: Asha Talambedu <atalambedu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3009638 Reviewed-by: Viswanath L <viswanathl@nvidia.com> Reviewed-by: Dara Ramesh <dramesh@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
167 lines
3.4 KiB
C
167 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include "dev.h"
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#include "dev-t264-aon.h"
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/* Defining offsets */
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#define AO_MISC_CPU_RESET_VECTOR_0 0x0
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#define AO_MISC_CPU_RUNSTALL_0 0x4
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#define AO_MISC_CPU_WFI_STATUS_0 0x8
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/* Defining fields */
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#define AO_MISC_CPU_SET_RUNSTALL_0 0x1
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#define AO_MISC_CPU_CLEAR_RUNSTALL_0 0x0
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int nvaon_os_t264_init(struct platform_device *pdev)
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{
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/* TBD */
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return 0;
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}
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static __attribute__((unused))
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int nvaon_t264_clocks_disable(struct platform_device *pdev)
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{
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/* TBD */
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return 0;
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}
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static __attribute__((unused))
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int nvaon_t264_clocks_enable(struct platform_device *pdev)
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{
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/* TBD */
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return 0;
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}
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#ifdef CONFIG_PM
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static int __nvaon_t264_runtime_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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int ret;
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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ret = nvaon_t264_clocks_enable(pdev);
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if (ret) {
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dev_dbg(dev, "failed in nvadsp_t264_clocks_enable\n");
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return ret;
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}
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return ret;
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}
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static int __nvaon_t264_runtime_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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return nvaon_t264_clocks_disable(pdev);
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}
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static int __nvaon_t264_runtime_idle(struct device *dev)
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{
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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return 0;
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}
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int nvaon_pm_t264_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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dev_dbg(dev, "at %s:%d\n", __func__, __LINE__);
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d->runtime_suspend = __nvaon_t264_runtime_suspend;
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d->runtime_resume = __nvaon_t264_runtime_resume;
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d->runtime_idle = __nvaon_t264_runtime_idle;
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return 0;
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}
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#endif /* CONFIG_PM */
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static int __set_boot_vec_t264(struct nvadsp_drv_data *d)
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{
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/* TBD */
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return 0;
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}
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static int __set_boot_freqs_t264(struct nvadsp_drv_data *d)
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{
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/* TBD */
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return 0;
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}
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static int __assert_t264_aon(struct nvadsp_drv_data *d)
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{
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void __iomem *cpu_config_base;
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u32 cpu_config;
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/* TBD: CPU assert */
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/* Assert RUNSTALL */
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cpu_config_base = d->base_regs[AO_MISC];
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cpu_config = AO_MISC_CPU_SET_RUNSTALL_0;
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writel(cpu_config, cpu_config_base + AO_MISC_CPU_RUNSTALL_0);
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return 0;
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}
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static int __deassert_t264_aon(struct nvadsp_drv_data *d)
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{
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void __iomem *cpu_config_base;
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u32 cpu_config;
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/* TBD: CPU deassert */
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/* Lift RUNSTALL */
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cpu_config_base = d->base_regs[AO_MISC];
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cpu_config = AO_MISC_CPU_CLEAR_RUNSTALL_0;
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writel(cpu_config, cpu_config_base + AO_MISC_CPU_RUNSTALL_0);
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return 0;
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}
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static int __map_hwmbox_interrupts(struct nvadsp_drv_data *d)
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{
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/* TBD: Map hwmbox interrupts to shared interrupt lines */
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return 0;
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}
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static bool __check_wfi_status(struct nvadsp_drv_data *d)
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{
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void __iomem *cpu_config_base;
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bool wfi_status = false;
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u8 cnt = 5;
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cpu_config_base = d->base_regs[AO_MISC];
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while (cnt > 0) {
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wfi_status = readl(cpu_config_base + AO_MISC_CPU_WFI_STATUS_0);
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if (wfi_status)
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return wfi_status;
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cnt--;
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}
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return wfi_status;
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}
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int nvaon_reset_t264_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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int ret = 0;
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d->assert_adsp = __assert_t264_aon;
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d->deassert_adsp = __deassert_t264_aon;
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d->adspall_rst = NULL; //TBD
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d->set_boot_vec = __set_boot_vec_t264;
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d->set_boot_freqs = __set_boot_freqs_t264;
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d->map_hwmbox_interrupts = __map_hwmbox_interrupts;
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d->check_wfi_status = __check_wfi_status;
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return ret;
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}
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