Files
linux-nv-oot/Documentation/devicetree/bindings/platform/tegra/mc-utils/nvidia,tegra264-mc.yaml
Mark Mendez a2ee9f655f PCT: Create devicetree validation schema
This is the output of the automated scripts created
to parse the dtb and dts files congruently

Jira ESDP-27666

Change-Id: Ic82a3f813bcbe6e78ba5f9b68875293c5d4bc6d7
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3274878
Tested-by: Mark Mendez <mmendez@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2025-07-24 10:19:12 +00:00

204 lines
6.9 KiB
YAML

# Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controller@8108020000/nvidia,tegra264-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: FIXME -- add title
maintainers:
- FIXME -- add maintainers
description: |
the compatability = nvidia,tegra264-mc is mentioned in the following drivers
- <TOP>/kernel/nvidia-oot/drivers/platform/tegra/mc-utils/mc-utils.c
The following nodes use this compatibility
- /bus@0/memory-controller@8108020000
select:
properties:
compatible:
minItems: 2
maxItems: 2
items:
enum:
- nvidia,tegra264-mc
- nvidia,tegra234-mc
required:
- compatible
properties:
reg:
$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
description: |
Registers are given by a tuple of two values:
- register address:
- register block size.
items:
minItems: 4
maxItems: 4
items:
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x81
maximum: 0x81
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x8020000
maximum: 0x8220000
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x0
maximum: 0x0
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x20000
maximum: 0x20000
reg-names:
$ref: "/schemas/types.yaml#/definitions/string-array"
items:
enum:
- broadcast
- ch0
- ch1
- ch2
- ch3
- ch4
- ch5
- ch6
- ch7
- ch8
- ch9
- ch10
- ch11
- ch12
- ch13
- ch14
- ch15
interrupts:
$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
description: |
Interrupts are give by a tuple of 3 values:
- interrupt specifier (GIC_SPI = 0, GIC_PPI = 1)
definitions in dt-bindings/interrupt-controller/arm-gic.h
- interrupt number
- trigger type (rising edge, falling edge, both, etc)
definitions in dt-bindings/interrupt-controller/irq.h
items:
items:
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x0
maximum: 0x0
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x8b
maximum: 0x387
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x4
maximum: 0x4
'#interconnect-cells':
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x1
maximum: 0x1
'#address-cells':
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x2
maximum: 0x2
'#size-cells':
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x2
maximum: 0x2
dma-ranges:
$ref: "/schemas/types.yaml#/definitions/uint32-matrix"
items:
minItems: 6
maxItems: 6
items:
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x0
maximum: 0x0
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x0
maximum: 0x0
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x0
maximum: 0x0
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x0
maximum: 0x0
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x100
maximum: 0x100
- $ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x0
maximum: 0x0
numa-node-id:
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0x0
maximum: 0x0
required:
- compatible
- reg
- interrupts
examples:
- |
memory-controller@8108020000 {
compatible = "nvidia,tegra264-mc",
"nvidia,tegra234-mc";
status = "disabled";
reg = <0x81 0x08020000 0x0 0x20000>,
<0x81 0x08040000 0x0 0x20000>,
<0x81 0x08060000 0x0 0x20000>,
<0x81 0x08080000 0x0 0x20000>,
<0x81 0x080a0000 0x0 0x20000>,
<0x81 0x080c0000 0x0 0x20000>,
<0x81 0x080e0000 0x0 0x20000>,
<0x81 0x08100000 0x0 0x20000>,
<0x81 0x08120000 0x0 0x20000>,
<0x81 0x08140000 0x0 0x20000>,
<0x81 0x08160000 0x0 0x20000>,
<0x81 0x08180000 0x0 0x20000>,
<0x81 0x081a0000 0x0 0x20000>,
<0x81 0x081c0000 0x0 0x20000>,
<0x81 0x081e0000 0x0 0x20000>,
<0x81 0x08200000 0x0 0x20000>,
<0x81 0x08220000 0x0 0x20000>;
reg-names = "broadcast, ch0, ch1, ch2, ch3",
"ch4, ch5, ch6, ch7, ch8, ch9, ch10",
"ch11, ch12, ch13, ch14, ch15";
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
#interconnect-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x81 0x08020000 0x81 0x08020000 0x0 0x20000>,
<0x81 0x08040000 0x81 0x08040000 0x0 0x20000>,
<0x81 0x080c0000 0x81 0x080c0000 0x0 0x20000>;
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
numa-node-id = <0x0>;
};