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git://nv-tegra.nvidia.com/linux-nv-oot.git
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681288f1be
Because of the way in which Makefile is defined for the drivers, each driver file is getting compliled as separate *.ko module. This results in loading of all the *.ko modules for maintaining the functionality. Current patch re-organises makefile and thus terga-alt structure, - utils/ : will provide all the helper functions, - machine_drivers/ : lists all the machine specific drivers we have, - tegra-alt/*.c : ahub module drivers, each would have a separate driver module, - include/ : all the local header files needed for driver modules Bug 200346429 Change-Id: Ic659879a0d6e8ef48b0d79b81059fba4c069591e Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1559745 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
482 lines
21 KiB
C
482 lines
21 KiB
C
/*
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* ahub_unit_fpga_clock.h
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*
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* Copyright (c) 2013-2017, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __AHUB_UNIT_FPGA_CLOCK_H__
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#define __AHUB_UNIT_FPGA_CLOCK_H__
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#define SYSTEM_FPGA 0
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#define DEBUG_FPGA 1
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#define APE_FPGA_MISC_CLK_SOURCE_I2C1_0 0x68
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#define APE_FPGA_MISC_CLK_SOURCE_I2S1_0 0x28
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#define APE_FPGA_MISC_CLK_SOURCE_I2S2_0 0x20
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#define APE_FPGA_MISC_CLK_SOURCE_I2S3_0 0x24
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#define APE_FPGA_MISC_CLK_SOURCE_I2S4_0 0x2c
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#define APE_FPGA_MISC_CLK_SOURCE_I2S5_0 0x30
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#define APE_FPGA_MISC_CLK_SOURCE_DMIC1_0 0x14
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#define I2C_I2C_CMD_ADDR0_0 0x4
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#define I2C_I2C_CNFG_0 0x0
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#define I2C_I2C_CMD_DATA1_0 0xc
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#define I2C_I2C_CONFIG_LOAD_0 0x8c
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#define I2C_I2C_STATUS_0 0x1c
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#define I2C_I2C_CMD_ADDR1_0 0x8
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#define I2C_I2C_CMD_DATA1_0 0xc
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#define I2C_I2C_CMD_DATA2_0 0x10
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0 0x1d8
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0 0x100
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0 0x104
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0 0x3bc
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0 0x3c0
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#define CLK_RST_CONTROLLER_RST_DEVICES_L_0 0x4
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0 0x10
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0 0x124
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#define PINMUX_AUX_GEN1_I2C_SDA_0 0x30c0
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#define PINMUX_AUX_GEN1_I2C_SCL_0 0x30bc
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#define PINMUX_AUX_DAP1_SCLK_0 0x3130
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#define PINMUX_AUX_DAP1_FS_0 0x3124
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#define PINMUX_AUX_DAP1_DIN_0 0x3128
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#define PINMUX_AUX_DAP1_DOUT_0 0x312c
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#define PINMUX_AUX_DAP2_SCLK_0 0x3140
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#define PINMUX_AUX_DAP2_FS_0 0x3134
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#define PINMUX_AUX_DAP2_DIN_0 0x3138
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#define PINMUX_AUX_DAP2_DOUT_0 0x313c
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#define PINMUX_AUX_DMIC1_CLK_0 0x30a4 /* DAP3_SCLK_0 */
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#define PINMUX_AUX_DMIC1_DAT_0 0x30a8 /* DAP3_FS_0 */
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#define PINMUX_AUX_DMIC2_CLK_0 0x30ac /* DAP3_DIN_0 */
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#define PINMUX_AUX_DMIC2_DAT_0 0x30b0 /* DAP3_DOUT_0 */
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#define PINMUX_AUX_GPIO_PK0_0 0x3254 /* DAP5 */
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#define PINMUX_AUX_GPIO_PK1_0 0x3258 /* DAP5 */
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#define PINMUX_AUX_GPIO_PK2_0 0x325c /* DAP5 */
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#define PINMUX_AUX_GPIO_PK3_0 0x3260 /* DAP5 */
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#define NV_ADDRESS_MAP_APE_AHUB_FPGA_CAR_BASE 1882050560
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#define NV_ADDRESS_MAP_APE_AHUB_FPGA_CAR_LIMIT 1882054655
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#define NV_ADDRESS_MAP_APE_AHUB_FPGA_CAR_SIZE 4096
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#define T210_NV_ADDRESS_MAP_APE_AHUB_FPGA_MISC_BASE 1882048512
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#define T186_NV_ADDRESS_MAP_APE_AHUB_FPGA_MISC_BASE 0x0290C800
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#define T210_NV_ADDRESS_MAP_APE_AHUB_FPGA_MISC_LIMIT 1882048767
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#define T186_NV_ADDRESS_MAP_APE_AHUB_FPGA_MISC_LIMIT 0x0290C8FF
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#define NV_ADDRESS_MAP_APE_AHUB_FPGA_MISC_SIZE 256
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#if SYSTEM_FPGA
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#define T210_NV_ADDRESS_MAP_APE_AHUB_I2C_BASE 0x7000c000
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#else
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#define T210_NV_ADDRESS_MAP_APE_AHUB_I2C_BASE 1882047744
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#define T186_NV_ADDRESS_MAP_APE_AHUB_I2C_BASE 0x0290c500
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#define NV_ADDRESS_MAP_APE_AHUB_GPIO_BASE 0x702DC700
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#define APE_AHUB_GPIO_CNF_0 0x0
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#define APE_AHUB_GPIO_OE_0 0x10
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#define APE_AHUB_GPIO_OUT_0 0x20
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#endif
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#define NV_ADDRESS_MAP_APE_AHUB_I2C_LIMIT 1882048255
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#define NV_ADDRESS_MAP_APE_AHUB_I2C_SIZE 512
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#define NV_ADDRESS_MAP_APB_PP_BASE 1879048192
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#define NV_ADDRESS_MAP_PPSB_CLK_RST_BASE 1610637312
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#define T210_NV_ADDRESS_MAP_APE_I2S5_BASE 0x702d1400
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#define T186_NV_ADDRESS_MAP_APE_I2S5_BASE 0x02901400
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#define I2S5_CYA_0 0xb0
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#define APE_FPGA_MISC_CLK_SOURCE_DSPK1_0 0x6c
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#define APE_FPGA_MISC_CLK_SOURCE_DSPK2_0 0x70
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#define CDCE906_04_0960_MHz 0
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#define CDCE906_06_1440_MHz 1
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#define CDCE906_08_1920_MHz 2
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#define CDCE906_11_2896_MHz 3
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#define CDCE906_12_2880_MHz 4
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#define CDCE906_16_3840_MHz 5
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#define CDCE906_22_5792_MHz 6
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#define CDCE906_24_5760_MHz 7
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#define CDCE906_09_2160_MHz 8
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#define CDCE906_16_9344_MHz 9
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#define CDCE906_18_4320_MHz 10
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#define CDCE906_33_8688_MHz 11
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#define CDCE906_36_8640_MHz 12
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#define MAX9485_DEVICE_ADDRESS 0x60
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#define MAX9485_MCLK_FREQ_163840 0x31
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#define MAX9485_MCLK_FREQ_112896 0x22
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#define MAX9485_MCLK_FREQ_122880 0x23
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#define MAX9485_MCLK_FREQ_225792 0x32
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#define MAX9485_MCLK_FREQ_245760 0x33
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enum AUDIO_DAC_DATAWIDTH{
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AUDIO_DAC_DATAWIDTH_16 = 3,
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AUDIO_DAC_DATAWIDTH_24 = 5
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};
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enum AUDIO_SAMPLE_RATE{
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AUDIO_SAMPLE_RATE_8_00 = 8000,
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AUDIO_SAMPLE_RATE_11_02 = 11020,
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AUDIO_SAMPLE_RATE_12_00 = 12000,
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AUDIO_SAMPLE_RATE_16_00 = 16000,
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AUDIO_SAMPLE_RATE_22_05 = 22050,
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AUDIO_SAMPLE_RATE_24_00 = 24000,
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AUDIO_SAMPLE_RATE_32_00 = 32000,
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AUDIO_SAMPLE_RATE_44_10 = 44100,
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AUDIO_SAMPLE_RATE_48_00 = 48000,
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AUDIO_SAMPLE_RATE_64_00 = 64000,
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AUDIO_SAMPLE_RATE_88_20 = 88200,
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AUDIO_SAMPLE_RATE_96_00 = 96000,
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AUDIO_SAMPLE_RATE_128_00 = 128000,
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AUDIO_SAMPLE_RATE_176_40 = 176000,
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AUDIO_SAMPLE_RATE_192_00 = 192000
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};
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enum I2S_ID{
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I2S1 = 0,
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I2S2,
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I2S3,
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I2S4,
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I2S5
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};
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enum AUDIO_MASTER_CLK_FREQ{
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CLK_OUT_3_0720_MHZ = 0,
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CLK_OUT_4_0960_MHZ,
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CLK_OUT_4_6080_MHZ,
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CLK_OUT_5_6448_MHZ,
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CLK_OUT_6_1440_MHZ,
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CLK_OUT_8_1920_MHZ,
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CLK_OUT_11_2896_MHZ,
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CLK_OUT_12_2888_MHZ,
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CLK_OUT_16_3840_MHZ,
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CLK_OUT_16_9344_MHZ,
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CLK_OUT_18_4320_MHZ,
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CLK_OUT_22_5792_MHZ,
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CLK_OUT_24_5760_MHZ,
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CLK_OUT_33_8688_MHZ,
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CLK_OUT_36_8640_MHZ,
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CLK_OUT_49_1520_MHZ,
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CLK_OUT_73_7280_MHZ,
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CLK_OUT_162_MHZ,
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TOTAL_CLK_OUT
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};
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enum AUDIO_CLOCK_GEN_SELECT{
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CLK_OUT_FROM_TEGRA,
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CLK_GEN_CDCE906,
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CLK_GEN_MAX9485
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};
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#define AD1937_X_ADDRESS 0x05
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#define AD1937_Y_ADDRESS 0x04
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#define AD1937_Z_ADDRESS 0x07
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#define AD1937_PLL_CLK_CTRL_0 0x00
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#define AD1937_PLL_CLK_CTRL_1 0x01
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#define AD1937_DAC_CTRL_0 0x02
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#define AD1937_DAC_CTRL_1 0x03
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#define AD1937_DAC_CTRL_2 0x04
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#define AD1937_DAC_MUTE_CTRL 0x05
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#define AD1937_DAC_VOL_CTRL_DAC1L 0x06
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#define AD1937_DAC_VOL_CTRL_DAC1R 0x07
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#define AD1937_DAC_VOL_CTRL_DAC2L 0x08
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#define AD1937_DAC_VOL_CTRL_DAC2R 0x09
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#define AD1937_DAC_VOL_CTRL_DAC3L 0x0a
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#define AD1937_DAC_VOL_CTRL_DAC3R 0x0b
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#define AD1937_DAC_VOL_CTRL_DAC4L 0x0c
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#define AD1937_DAC_VOL_CTRL_DAC4R 0x0d
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#define AD1937_ADC_CTRL_0 0x0e
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#define AD1937_ADC_CTRL_1 0x0f
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#define AD1937_ADC_CTRL_2 0x10
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#define AD1937_PLL_CLK_CTRL_0_PWR_MASK (1 << 0)
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#define AD1937_PLL_CLK_CTRL_0_PWR_ON (0 << 0)
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#define AD1937_PLL_CLK_CTRL_0_PWR_OFF (1 << 0)
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#define AD1937_PLL_CLK_CTRL_0_MCLKI_MASK (3 << 1)
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#define AD1937_PLL_CLK_CTRL_0_MCLKI_256 (0 << 1)
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#define AD1937_PLL_CLK_CTRL_0_MCLKI_384 (1 << 1)
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#define AD1937_PLL_CLK_CTRL_0_MCLKI_512 (2 << 1)
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#define AD1937_PLL_CLK_CTRL_0_MCLKI_768 (3 << 1)
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#define AD1937_PLL_CLK_CTRL_0_MCLKO_MASK (3 << 3)
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#define AD1937_PLL_CLK_CTRL_0_MCLKO_XTAL (0 << 3)
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#define AD1937_PLL_CLK_CTRL_0_MCLKO_256 (1 << 3)
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#define AD1937_PLL_CLK_CTRL_0_MCLKO_512 (2 << 3)
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#define AD1937_PLL_CLK_CTRL_0_MCLKO_OFF (3 << 3)
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#define AD1937_PLL_CLK_CTRL_0_PLL_INPUT_MASK (3 << 5)
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#define AD1937_PLL_CLK_CTRL_0_PLL_INPUT_MCLKI (0 << 5)
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#define AD1937_PLL_CLK_CTRL_0_PLL_INPUT_DLRCLK (1 << 5)
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#define AD1937_PLL_CLK_CTRL_0_PLL_INPUT_ALRCLK (2 << 5)
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#define AD1937_PLL_CLK_CTRL_0_INTERNAL_MASTER_CLK_MASK (1 << 7)
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#define AD1937_PLL_CLK_CTRL_0_INTERNAL_MASTER_CLK_DISABLE (0 << 7)
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#define AD1937_PLL_CLK_CTRL_0_INTERNAL_MASTER_CLK_ENABLE (1 << 7)
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#define AD1937_PLL_CLK_CTRL_1_DAC_CLK_MASK (1 << 0)
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#define AD1937_PLL_CLK_CTRL_1_DAC_CLK_PLL (0 << 0)
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#define AD1937_PLL_CLK_CTRL_1_DAC_CLK_MCLK (1 << 0)
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#define AD1937_PLL_CLK_CTRL_1_ADC_CLK_MASK (1 << 1)
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#define AD1937_PLL_CLK_CTRL_1_ADC_CLK_PLL (0 << 1)
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#define AD1937_PLL_CLK_CTRL_1_ADC_CLK_MCLK (1 << 1)
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#define AD1937_PLL_CLK_CTRL_1_VREF_MASK (1 << 2)
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#define AD1937_PLL_CLK_CTRL_1_VREF_ENABLE (0 << 2)
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#define AD1937_PLL_CLK_CTRL_1_VREF_DISABLE (1 << 2)
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#define AD1937_PLL_CLK_CTRL_1_PLL_MASK (1 << 3)
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#define AD1937_PLL_CLK_CTRL_1_PLL_NOT_LOCKED (0 << 3)
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#define AD1937_PLL_CLK_CTRL_1_PLL_LOCKED (1 << 3)
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#define AD1937_DAC_CTRL_0_PWR_MASK (1 << 0)
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#define AD1937_DAC_CTRL_0_PWR_ON (0 << 0)
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#define AD1937_DAC_CTRL_0_PWR_OFF (1 << 0)
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#define AD1937_DAC_CTRL_0_SAMPLE_RATE_MASK (3 << 1)
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#define AD1937_DAC_CTRL_0_SAMPLE_RATE_32_44_1_48_KHZ (0 << 1)
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#define AD1937_DAC_CTRL_0_SAMPLE_RATE_64_88_2_96_KHZ (1 << 1)
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#define AD1937_DAC_CTRL_0_SAMPLE_RATE_128_176_4_192_KHZ (2 << 1)
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#define AD1937_DAC_CTRL_0_DSDATA_DELAY_MASK (7 << 3)
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#define AD1937_DAC_CTRL_0_DSDATA_DELAY_1 (0 << 3)
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#define AD1937_DAC_CTRL_0_DSDATA_DELAY_0 (1 << 3)
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#define AD1937_DAC_CTRL_0_DSDATA_DELAY_8 (2 << 3)
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#define AD1937_DAC_CTRL_0_DSDATA_DELAY_12 (3 << 3)
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#define AD1937_DAC_CTRL_0_DSDATA_DELAY_16 (4 << 3)
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#define AD1937_DAC_CTRL_0_FMT_MASK (3 << 6)
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#define AD1937_DAC_CTRL_0_FMT_STEREO (0 << 6)
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#define AD1937_DAC_CTRL_0_FMT_TDM_SINGLE_LINE (1 << 6)
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#define AD1937_DAC_CTRL_0_FMT_TDM_AUX (2 << 6)
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#define AD1937_DAC_CTRL_0_FMT_TDM_DUAL_LINE (3 << 6)
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#define AD1937_DAC_CTRL_1_DBCLK_ACTIVE_EDGE_MASK (1 << 0)
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#define AD1937_DAC_CTRL_1_DBCLK_ACTIVE_EDGE_MIDCYCLE (0 << 0)
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#define AD1937_DAC_CTRL_1_DBCLK_ACTIVE_EDGE_PIPELINE (1 << 0)
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#define AD1937_DAC_CTRL_1_DBCLK_PER_FRAME_MASK (3 << 1)
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#define AD1937_DAC_CTRL_1_DBCLK_PER_FRAME_64 (0 << 1)
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#define AD1937_DAC_CTRL_1_DBCLK_PER_FRAME_128 (1 << 1)
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#define AD1937_DAC_CTRL_1_DBCLK_PER_FRAME_256 (2 << 1)
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#define AD1937_DAC_CTRL_1_DBCLK_PER_FRAME_512 (3 << 1)
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#define AD1937_DAC_CTRL_1_DLRCLK_POLARITY_MASK (1 << 3)
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#define AD1937_DAC_CTRL_1_DLRCLK_POLARITY_LEFT_LOW (0 << 3)
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#define AD1937_DAC_CTRL_1_DLRCLK_POLARITY_LEFT_HIGH (1 << 3)
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#define AD1937_DAC_CTRL_1_DLRCLK_MASK (1 << 4)
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#define AD1937_DAC_CTRL_1_DLRCLK_SLAVE (0 << 4)
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#define AD1937_DAC_CTRL_1_DLRCLK_MASTER (1 << 4)
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#define AD1937_DAC_CTRL_1_DBCLK_MASK (1 << 5)
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#define AD1937_DAC_CTRL_1_DBCLK_SLAVE (0 << 5)
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#define AD1937_DAC_CTRL_1_DBCLK_MASTER (1 << 5)
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#define AD1937_DAC_CTRL_1_DBCLK_SOURCE_MASK (1 << 6)
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#define AD1937_DAC_CTRL_1_DBCLK_SOURCE_DBCLK_PIN (0 << 6)
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#define AD1937_DAC_CTRL_1_DBCLK_SOURCE_INTERNAL (1 << 6)
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#define AD1937_DAC_CTRL_1_DBCLK_POLARITY_MASK (1 << 7)
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#define AD1937_DAC_CTRL_1_DBCLK_POLARITY_NORMAL (0 << 7)
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#define AD1937_DAC_CTRL_1_DBCLK_POLARITY_INVERTED (1 << 7)
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#define AD1937_DAC_CTRL_2_MASTER_MASK (1 << 0)
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#define AD1937_DAC_CTRL_2_MASTER_UNMUTE (0 << 0)
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#define AD1937_DAC_CTRL_2_MASTER_MUTE (1 << 0)
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#define AD1937_DAC_CTRL_2_DEEMPHASIS_MASK (3 << 1)
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#define AD1937_DAC_CTRL_2_DEEMPHASIS_FLAT (0 << 1)
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#define AD1937_DAC_CTRL_2_DEEMPHASIS_48_KHZ (1 << 1)
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#define AD1937_DAC_CTRL_2_DEEMPHASIS_44_1_KHZ (2 << 1)
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#define AD1937_DAC_CTRL_2_DEEMPHASIS_32_KHZ (3 << 1)
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#define AD1937_DAC_CTRL_2_WORD_WIDTH_MASK (3 << 3)
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#define AD1937_DAC_CTRL_2_WORD_WIDTH_24_BITS (0 << 3)
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#define AD1937_DAC_CTRL_2_WORD_WIDTH_20_BITS (1 << 3)
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#define AD1937_DAC_CTRL_2_WORD_WIDTH_16_BITS (3 << 3)
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#define AD1937_DAC_CTRL_2_DAC_OUTPUT_POLARITY_MASK (1 << 5)
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#define AD1937_DAC_CTRL_2_DAC_OUTPUT_POLARITY_NORMAL (0 << 5)
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#define AD1937_DAC_CTRL_2_DAC_OUTPUT_POLARITY_INVERTED (1 << 5)
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#define AD1937_DAC_MUTE_CTRL_DAC1L_MASK (1 << 0)
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#define AD1937_DAC_MUTE_CTRL_DAC1L_UNMUTE (0 << 0)
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#define AD1937_DAC_MUTE_CTRL_DAC1L_MUTE (1 << 0)
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#define AD1937_DAC_MUTE_CTRL_DAC1R_MASK (1 << 1)
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#define AD1937_DAC_MUTE_CTRL_DAC1R_UNMUTE (0 << 1)
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#define AD1937_DAC_MUTE_CTRL_DAC1R_MUTE (1 << 1)
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#define AD1937_DAC_MUTE_CTRL_DAC2L_MASK (1 << 2)
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#define AD1937_DAC_MUTE_CTRL_DAC2L_UNMUTE (0 << 2)
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#define AD1937_DAC_MUTE_CTRL_DAC2L_MUTE (1 << 2)
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#define AD1937_DAC_MUTE_CTRL_DAC2R_MASK (1 << 3)
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#define AD1937_DAC_MUTE_CTRL_DAC2R_UNMUTE (0 << 3)
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#define AD1937_DAC_MUTE_CTRL_DAC2R_MUTE (1 << 3)
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#define AD1937_DAC_MUTE_CTRL_DAC3L_MASK (1 << 4)
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#define AD1937_DAC_MUTE_CTRL_DAC3L_UNMUTE (0 << 4)
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#define AD1937_DAC_MUTE_CTRL_DAC3L_MUTE (1 << 4)
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#define AD1937_DAC_MUTE_CTRL_DAC3R_MASK (1 << 5)
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#define AD1937_DAC_MUTE_CTRL_DAC3R_UNMUTE (0 << 5)
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#define AD1937_DAC_MUTE_CTRL_DAC3R_MUTE (1 << 5)
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#define AD1937_DAC_MUTE_CTRL_DAC4L_MASK (1 << 6)
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#define AD1937_DAC_MUTE_CTRL_DAC4L_UNMUTE (0 << 6)
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#define AD1937_DAC_MUTE_CTRL_DAC4L_MUTE (1 << 6)
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#define AD1937_DAC_MUTE_CTRL_DAC4R_MASK (1 << 7)
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#define AD1937_DAC_MUTE_CTRL_DAC4R_UNMUTE (0 << 7)
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#define AD1937_DAC_MUTE_CTRL_DAC4R_MUTE (1 << 7)
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#define AD1937_DAC_VOL_CTRL_DAC1L_MASK (0xff << 0)
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#define AD1937_DAC_VOL_CTRL_DAC1R_MASK (0xff << 0)
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#define AD1937_DAC_VOL_CTRL_DAC2L_MASK (0xff << 0)
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#define AD1937_DAC_VOL_CTRL_DAC2R_MASK (0xff << 0)
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#define AD1937_DAC_VOL_CTRL_DAC3L_MASK (0xff << 0)
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#define AD1937_DAC_VOL_CTRL_DAC3R_MASK (0xff << 0)
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#define AD1937_DAC_VOL_CTRL_DAC4L_MASK (0xff << 0)
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#define AD1937_DAC_VOL_CTRL_DAC4R_MASK (0xff << 0)
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#define AD1937_ADC_CTRL_0_PWR_MASK (1 << 0)
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#define AD1937_ADC_CTRL_0_PWR_ON (0 << 0)
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#define AD1937_ADC_CTRL_0_PWR_OFF (1 << 0)
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#define AD1937_ADC_CTRL_0_HIGH_PASS_FILTER_MASK (1 << 1)
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#define AD1937_ADC_CTRL_0_HIGH_PASS_FILTER_OFF (0 << 1)
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#define AD1937_ADC_CTRL_0_HIGH_PASS_FILTER_ON (1 << 1)
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#define AD1937_ADC_CTRL_0_ADC1L_MASK (1 << 2)
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#define AD1937_ADC_CTRL_0_ADC1L_UNMUTE (0 << 2)
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#define AD1937_ADC_CTRL_0_ADC1L_MUTE (1 << 2)
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#define AD1937_ADC_CTRL_0_ADC1R_MASK (1 << 3)
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#define AD1937_ADC_CTRL_0_ADC1R_UNMUTE (0 << 3)
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#define AD1937_ADC_CTRL_0_ADC1R_MUTE (1 << 3)
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#define AD1937_ADC_CTRL_0_ADC2L_MASK (1 << 4)
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#define AD1937_ADC_CTRL_0_ADC2L_UNMUTE (0 << 4)
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#define AD1937_ADC_CTRL_0_ADC2L_MUTE (1 << 4)
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#define AD1937_ADC_CTRL_0_ADC2R_MASK (1 << 5)
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#define AD1937_ADC_CTRL_0_ADC2R_UNMUTE (0 << 5)
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#define AD1937_ADC_CTRL_0_ADC2R_MUTE (1 << 5)
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#define AD1937_ADC_CTRL_0_SAMPLE_RATE_MASK (3 << 6)
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#define AD1937_ADC_CTRL_0_SAMPLE_RATE_32_44_1_48_KHZ (0 << 6)
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#define AD1937_ADC_CTRL_0_SAMPLE_RATE_64_88_2_96_KHZ (1 << 6)
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#define AD1937_ADC_CTRL_0_SAMPLE_RATE_128_176_4_192_KHZ (2 << 6)
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#define AD1937_ADC_CTRL_1_WORD_WIDTH_MASK (3 << 0)
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#define AD1937_ADC_CTRL_1_WORD_WIDTH_24_BITS (0 << 0)
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#define AD1937_ADC_CTRL_1_WORD_WIDTH_20_BITS (1 << 0)
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#define AD1937_ADC_CTRL_1_WORD_WIDTH_16_BITS (3 << 0)
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#define AD1937_ADC_CTRL_1_ASDATA_DELAY_MASK (7 << 2)
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#define AD1937_ADC_CTRL_1_ASDATA_DELAY_1 (0 << 2)
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#define AD1937_ADC_CTRL_1_ASDATA_DELAY_0 (1 << 2)
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#define AD1937_ADC_CTRL_1_ASDATA_DELAY_8 (2 << 2)
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#define AD1937_ADC_CTRL_1_ASDATA_DELAY_12 (3 << 2)
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#define AD1937_ADC_CTRL_1_ASDATA_DELAY_16 (4 << 2)
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#define AD1937_ADC_CTRL_1_FMT_MASK (3 << 5)
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#define AD1937_ADC_CTRL_1_FMT_STEREO (0 << 5)
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#define AD1937_ADC_CTRL_1_FMT_TDM_SINGLE_LINE (1 << 5)
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#define AD1937_ADC_CTRL_1_FMT_TDM_AUX (2 << 5)
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#define AD1937_ADC_CTRL_1_ABCLK_ACTIVE_EDGE_MASK (1 << 7)
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#define AD1937_ADC_CTRL_1_ABCLK_ACTIVE_EDGE_MIDCYCLE (0 << 7)
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#define AD1937_ADC_CTRL_1_ABCLK_ACTIVE_EDGE_PIPELINE (1 << 7)
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#define AD1937_ADC_CTRL_2_ALRCLK_FMT_MASK (1 << 0)
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#define AD1937_ADC_CTRL_2_ALRCLK_FMT_50_50 (0 << 0)
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#define AD1937_ADC_CTRL_2_ALRCLK_FMT_PULSE (1 << 0)
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#define AD1937_ADC_CTRL_2_ABCLK_POLARITY_MASK (1 << 1)
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#define AD1937_ADC_CTRL_2_ABCLK_POLARITY_FALLING_EDGE (0 << 1)
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#define AD1937_ADC_CTRL_2_ABCLK_POLARITY_RISING_EDGE (1 << 1)
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#define AD1937_ADC_CTRL_2_ALRCLK_POLARITY_MASK (1 << 2)
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#define AD1937_ADC_CTRL_2_ALRCLK_POLARITY_LEFT_LOW (0 << 2)
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#define AD1937_ADC_CTRL_2_ALRCLK_POLARITY_LEFT_HIGH (1 << 2)
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#define AD1937_ADC_CTRL_2_ALRCLK_MASK (1 << 3)
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#define AD1937_ADC_CTRL_2_ALRCLK_SLAVE (0 << 3)
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#define AD1937_ADC_CTRL_2_ALRCLK_MASTER (1 << 3)
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#define AD1937_ADC_CTRL_2_ABCLK_PER_FRAME_MASK (3 << 4)
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#define AD1937_ADC_CTRL_2_ABCLK_PER_FRAME_64 (0 << 4)
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#define AD1937_ADC_CTRL_2_ABCLK_PER_FRAME_128 (1 << 4)
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#define AD1937_ADC_CTRL_2_ABCLK_PER_FRAME_256 (2 << 4)
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#define AD1937_ADC_CTRL_2_ABCLK_PER_FRAME_512 (3 << 4)
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#define AD1937_ADC_CTRL_2_ABCLK_MASK (1 << 6)
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#define AD1937_ADC_CTRL_2_ABCLK_SLAVE (0 << 6)
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#define AD1937_ADC_CTRL_2_ABCLK_MASTER (1 << 6)
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#define AD1937_ADC_CTRL_2_ABCLK_SOURCE_MASK (1 << 7)
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#define AD1937_ADC_CTRL_2_ABCLK_SOURCE_ABCLK_PIN (0 << 7)
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#define AD1937_ADC_CTRL_2_ABCLK_SOURCE_INTERNAL (1 << 7)
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#define AUDIO_CODEC_SLAVE_MODE 1
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#define AUDIO_CODEC_MASTER_MODE 0
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#define AUDIO_DAC_MASTER_MODE 1
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#define AUDIO_DAC_SLAVE_MODE 0
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#define I2S_DATAWIDTH_04 0
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#define I2S_DATAWIDTH_08 1
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#define I2S_DATAWIDTH_12 2
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#define I2S_DATAWIDTH_16 3
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#define I2S_DATAWIDTH_20 4
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#define I2S_DATAWIDTH_24 5
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#define I2S_DATAWIDTH_28 6
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#define I2S_DATAWIDTH_32 7
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#define AD1937_MCLK_PLL_INTERNAL_MODE 0
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#define AD1937_MCLK_DIRECT_MODE 1
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enum AUDIO_INTERFACE_FORMAT{
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AUDIO_INTERFACE_I2S_FORMAT,
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AUDIO_INTERFACE_LJM_FORMAT,
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AUDIO_INTERFACE_RJM_FORMAT,
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AUDIO_INTERFACE_DSP_FORMAT,
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AUDIO_INTERFACE_PCM_FORMAT,
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AUDIO_INTERFACE_NW_FORMAT,
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AUDIO_INTERFACE_TDM_FORMAT,
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AUDIO_INTERFACE_TOTAL_FORMAT
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};
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typedef struct AD1937_EXTRA_INFO{
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unsigned int codecId;
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unsigned int clkgenId;
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unsigned int dacMasterEn;
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unsigned int daisyEn;
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unsigned int mclk_mode;
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} AD1937_EXTRA_INFO;
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struct ahub_unit_fpga {
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unsigned int configured;
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void __iomem *ape_fpga_misc_base;
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void __iomem *ape_fpga_misc_i2s_clk_base[5];
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void __iomem *ape_i2c_base;
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void __iomem *pinmux_base;
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void __iomem *ape_gpio_base;
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void __iomem *rst_clk_base;
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void __iomem *i2s5_cya_base;
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};
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void i2c_write(u32 addr, u32 regAddrr, u32 regData, u32 NoBytes);
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u32 i2c_read(u32 addr, u32 regAddrr);
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void i2s_clk_divider(u32 i2s, u32 Divider);
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void i2c_clk_divider(u32 Divider);
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void program_max_codec(void);
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void program_cdc_pll(u32 PLLno, u32 Freq);
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void i2s_clk_setup(u32 i2s, u32 source, u32 divider);
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void i2c_pinmux_setup(void);
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void i2c_clk_setup(u32 divider);
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void i2s_pinmux_setup(u32 i2s, u32 i2s_b);
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void program_io_expander(void);
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void program_dmic_gpio(void);
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void program_dmic_clk(int dmic_clk);
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void SetMax9485(int freq);
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void ahub_unit_fpga_init_t210(void);
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void ahub_unit_fpga_init_t186(void);
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void ahub_unit_fpga_deinit(void);
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struct ahub_unit_fpga *get_ahub_unit_fpga_private(void);
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void program_dspk_clk(int dspk_clk);
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|
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void OnAD1937CaptureAndPlayback(int mode,
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int codec_data_format,
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|
int codec_data_width,
|
|
int bitSize,
|
|
int polarity,
|
|
int bitclkInv,
|
|
int frameRate,
|
|
AD1937_EXTRA_INFO * extra_info);
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|
#endif
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