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685eb2c8d2
Add host1x05 version and fill in the h/w details in host1x05_info Add all the hardware accessors for T186 (channel, sync, uclass accessors) Add hardware support files for host1x channel, syncpoints, cdma, pushbuffer, interrupt, and debug support Keep gather filter disabled Things working with this : - cdma operations - basic channel job submit path - syncpoint support - syncpoint interrupt mechanism - debug dump With this support, below tests pass for VIC client $nvrm_channel channel_Basic $nvrm_channel --module=vic Bug 1704301 Change-Id: I7d97560cb1e3a57733fa0853936b0783c71b7060 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1021434 GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
158 lines
5.1 KiB
C
158 lines
5.1 KiB
C
/*
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* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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* Function naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef HOST1X_HW_HOST1X05_UCLASS_H
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#define HOST1X_HW_HOST1X05_UCLASS_H
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static inline u32 host1x_uclass_incr_syncpt_r(void)
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{
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return 0x0;
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}
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#define HOST1X_UCLASS_INCR_SYNCPT \
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host1x_uclass_incr_syncpt_r()
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static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
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{
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return (v & 0xff) << 10;
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}
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#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
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host1x_uclass_incr_syncpt_cond_f(v)
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static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
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{
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return (v & 0x3ff) << 0;
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}
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#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
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host1x_uclass_incr_syncpt_indx_f(v)
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static inline u32 host1x_uclass_load_syncpt_payload_32_r(void)
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{
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return 0x4e;
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}
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#define HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32 \
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host1x_uclass_load_syncpt_payload_32_r()
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static inline u32 host1x_uclass_wait_syncpt_32_r(void)
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{
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return 0x50;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_32 \
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host1x_uclass_wait_syncpt_32_r()
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static inline u32 host1x_uclass_wait_syncpt_r(void)
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{
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return 0x8;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT \
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host1x_uclass_wait_syncpt_r()
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static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
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{
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return (v & 0xff) << 24;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
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host1x_uclass_wait_syncpt_indx_f(v)
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static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
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{
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return (v & 0xffffff) << 0;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
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host1x_uclass_wait_syncpt_thresh_f(v)
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static inline u32 host1x_uclass_wait_syncpt_base_r(void)
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{
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return 0x9;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
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host1x_uclass_wait_syncpt_base_r()
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static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
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{
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return (v & 0x3ff) << 22;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
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host1x_uclass_wait_syncpt_base_indx_f(v)
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static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
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{
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return (v & 0x3f) << 16;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
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host1x_uclass_wait_syncpt_base_base_indx_f(v)
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static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
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{
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return (v & 0xffff) << 0;
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}
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#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
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host1x_uclass_wait_syncpt_base_offset_f(v)
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static inline u32 host1x_uclass_load_syncpt_base_r(void)
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{
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return 0xb;
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}
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#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
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host1x_uclass_load_syncpt_base_r()
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static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
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{
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return (v & 0xff) << 24;
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}
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#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
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host1x_uclass_load_syncpt_base_base_indx_f(v)
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static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
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{
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return (v & 0xffffff) << 0;
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}
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#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
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host1x_uclass_load_syncpt_base_value_f(v)
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static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
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{
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return (v & 0xff) << 24;
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}
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#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
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host1x_uclass_incr_syncpt_base_base_indx_f(v)
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static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
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{
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return (v & 0xffffff) << 0;
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}
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#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
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host1x_uclass_incr_syncpt_base_offset_f(v)
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#endif
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