mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-24 18:21:35 +03:00
25bc2a3b96
Remove macro-protected dead code. NVMAP_LOADABLE_MODULE enables NvMap as an OOT module, while NVMAP_UPSTREAM_KERNEL is a config for kstable/OOT kernel. For Kernel 5.10+ both are always defined, So the related macro protected code can be safely removed. Bug 4479135 Change-Id: I792f1cb2c54fd21bcf0e73ffc52e46e4efd47862 Signed-off-by: Yash Bhatt <ybhatt@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3079420 Reviewed-by: Ashish Mhetre <amhetre@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
200 lines
4.5 KiB
ArmAsm
200 lines
4.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2021-2024, NVIDIA CORPORATION. All rights reserved.
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* Derived from Linux kernel source file arch/arm64/mm/cache.S
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*
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* Cache maintenance
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*/
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <linux/version.h>
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#include <asm/assembler.h>
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#include <asm/cpufeature.h>
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#include <asm/alternative.h>
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#include <asm/asm-uaccess.h>
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/*
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* invalidate_icache_range(start,end)
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*
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* Ensure that the I cache is invalid within specified region.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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SYM_FUNC_START(invalidate_icache_range)
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alternative_if ARM64_HAS_CACHE_DIC
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mov x0, xzr
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isb
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ret
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alternative_else_nop_endif
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uaccess_ttbr0_enable x2, x3, x4
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invalidate_icache_by_line x0, x1, x2, x3, 2f
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mov x0, xzr
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1:
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uaccess_ttbr0_disable x1, x2
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ret
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2:
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mov x0, #-EFAULT
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b 1b
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SYM_FUNC_END(invalidate_icache_range)
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/*
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* __flush_dcache_area(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned and invalidated to the PoC.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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SYM_FUNC_START(__flush_dcache_area)
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add x1, x0, x1
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dcache_by_line_op civac, sy, x0, x1, x2, x3
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ret
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SYM_FUNC_END(__flush_dcache_area)
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/*
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* __clean_dcache_area_pou(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned to the PoU.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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SYM_FUNC_START(__clean_dcache_area_pou)
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alternative_if ARM64_HAS_CACHE_IDC
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dsb ishst
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ret
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alternative_else_nop_endif
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add x1, x0, x1
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dcache_by_line_op cvau, ish, x0, x1, x2, x3
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ret
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SYM_FUNC_END(__clean_dcache_area_pou)
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/*
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* __inval_dcache_area(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are invalidated. Any partial lines at the ends of the interval are
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* also cleaned to PoC to prevent data loss.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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SYM_FUNC_START_LOCAL(__dma_inv_area)
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SYM_FUNC_START(__inval_dcache_area)
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/* FALLTHROUGH */
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/*
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* __dma_inv_area(start, size)
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* - start - virtual start address of region
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* - size - size in question
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*/
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add x1, x1, x0
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dcache_line_size x2, x3
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sub x3, x2, #1
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tst x1, x3 // end cache line aligned?
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bic x1, x1, x3
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b.eq 1f
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dc civac, x1 // clean & invalidate D / U line
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1: tst x0, x3 // start cache line aligned?
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bic x0, x0, x3
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b.eq 2f
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dc civac, x0 // clean & invalidate D / U line
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b 3f
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2: dc ivac, x0 // invalidate D / U line
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3: add x0, x0, x2
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cmp x0, x1
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b.lo 2b
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dsb sy
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ret
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SYM_FUNC_END(__inval_dcache_area)
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SYM_FUNC_END(__dma_inv_area)
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/*
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* __clean_dcache_area_poc(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned to the PoC.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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SYM_FUNC_START_LOCAL(__dma_clean_area)
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SYM_FUNC_START(__clean_dcache_area_poc)
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/* FALLTHROUGH */
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/*
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* __dma_clean_area(start, size)
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* - start - virtual start address of region
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* - size - size in question
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*/
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add x1, x0, x1
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dcache_by_line_op cvac, sy, x0, x1, x2, x3
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ret
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SYM_FUNC_END(__clean_dcache_area_poc)
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SYM_FUNC_END(__dma_clean_area)
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/*
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* __clean_dcache_area_pop(kaddr, size)
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*
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* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
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* are cleaned to the PoP.
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*
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* - kaddr - kernel address
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* - size - size in question
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*/
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SYM_FUNC_START(__clean_dcache_area_pop)
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alternative_if_not ARM64_HAS_DCPOP
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b __clean_dcache_area_poc
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alternative_else_nop_endif
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add x1, x0, x1
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dcache_by_line_op cvap, sy, x0, x1, x2, x3
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ret
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SYM_FUNC_END(__clean_dcache_area_pop)
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/*
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* __dma_flush_area(start, size)
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*
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* clean & invalidate D / U line
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*
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* - start - virtual start address of region
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* - size - size in question
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*/
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SYM_FUNC_START(__dma_flush_area)
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add x1, x0, x1
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dcache_by_line_op civac, sy, x0, x1, x2, x3
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ret
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SYM_FUNC_END(__dma_flush_area)
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/*
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* __dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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SYM_FUNC_START(__dma_map_area)
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cmp w2, #DMA_FROM_DEVICE
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b.eq __dma_inv_area
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b __dma_clean_area
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SYM_FUNC_END(__dma_map_area)
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/*
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* __dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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SYM_FUNC_START(__dma_unmap_area)
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cmp w2, #DMA_TO_DEVICE
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b.ne __dma_inv_area
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ret
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SYM_FUNC_END(__dma_unmap_area)
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