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6b98f0a740
AHUB and few components have been pushed for upstream review. Though the changes are still under review, we can leverage the work done on upstream 5.x and use the same here on 5.4 kernel. This helps to align the downstream code. Any changes that happen because of upstream review can be cherry picked here. If we plan for any downstream changes, upstream patch needs to be pushed to keep the code in sync. As of today current snapshot is pulled from v3 of AHUB series, http://patchwork.ozlabs.org/project/linux-tegra/list/?series=159664 Above series was worked on later versions of linux-next and hence following are the changes required for porting back on 5.4 * tegra_pcm_new() and tegra_pcm_free() are exposed from tegra_pcm.c and component driver callbacks use these. * Callback functions required for snd_pcm_ops in component driver are implemented by tegra_pcm.c * With this ADMAIF driver need not register platform device with ASoC core. For components (AHUB, ADMAIF, I2S, DMIC and DSPK) the downsream code differs in few aspects from the code that was pushed for v3. Some of them are listed below. * I2S driver in downstream implements startup()/shutdown() calls for DAI, which does some setup related to pinconfig and regulators. The same is true for DMIC and DSPK drivers as well. * Downstream ADMAIF drivers makes bandwidth requests in startup/shutdown() calls and has helper function for dumping registers. It also has additional DAI interfaces which are used for ADSP audio. * Downstream AHUB driver has DAI interfaces for connecting to all other modules. These differences will be cherry-picked as and when it is necessary. Bug 2845498 Change-Id: Id374967ecae26f6b7334a959fb23308d383c15f2 Signed-off-by: Sameer Pujar <spujar@nvidia.com>
74 lines
1.8 KiB
C
74 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra186_dspk.h - Definitions for Tegra186 DSPK driver
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*
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* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA186_DSPK_H__
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#define __TEGRA186_DSPK_H__
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/* Register offsets from DSPK BASE */
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#define TEGRA186_DSPK_RX_STATUS 0x0c
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#define TEGRA186_DSPK_RX_INT_STATUS 0x10
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#define TEGRA186_DSPK_RX_INT_MASK 0x14
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#define TEGRA186_DSPK_RX_INT_SET 0x18
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#define TEGRA186_DSPK_RX_INT_CLEAR 0x1c
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#define TEGRA186_DSPK_RX_CIF_CTRL 0x20
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#define TEGRA186_DSPK_ENABLE 0x40
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#define TEGRA186_DSPK_SOFT_RESET 0x44
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#define TEGRA186_DSPK_CG 0x48
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#define TEGRA186_DSPK_STATUS 0x4c
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#define TEGRA186_DSPK_INT_STATUS 0x50
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#define TEGRA186_DSPK_CORE_CTRL 0x60
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#define TEGRA186_DSPK_CODEC_CTRL 0x64
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/* DSPK CORE CONTROL fields */
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#define CH_SEL_SHIFT 8
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#define TEGRA186_DSPK_CHANNEL_SELECT_MASK (0x3 << CH_SEL_SHIFT)
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#define DSPK_OSR_SHIFT 4
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#define TEGRA186_DSPK_OSR_MASK (0x3 << DSPK_OSR_SHIFT)
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#define LRSEL_POL_SHIFT 0
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#define TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT)
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#define TEGRA186_DSPK_RX_FIFO_DEPTH 64
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#define DSPK_OSR_FACTOR 32
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/* DSPK interface clock ratio */
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#define DSPK_CLK_RATIO 4
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enum tegra_dspk_osr {
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DSPK_OSR_32,
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DSPK_OSR_64,
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DSPK_OSR_128,
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DSPK_OSR_256,
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};
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enum tegra_dspk_ch_sel {
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DSPK_CH_SELECT_LEFT,
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DSPK_CH_SELECT_RIGHT,
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DSPK_CH_SELECT_STEREO,
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};
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enum tegra_dspk_lrsel {
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DSPK_LRSEL_LEFT,
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DSPK_LRSEL_RIGHT,
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};
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struct tegra186_dspk {
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unsigned int rx_fifo_th;
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unsigned int osr_val;
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unsigned int lrsel;
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unsigned int srate_override;
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unsigned int audio_ch_override;
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unsigned int ch_sel; /* Used for client channel override */
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unsigned int audio_fmt_override;
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unsigned int mono_to_stereo;
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unsigned int stereo_to_mono;
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struct clk *clk_dspk;
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struct regmap *regmap;
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};
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#endif
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