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6b98f0a740
AHUB and few components have been pushed for upstream review. Though the changes are still under review, we can leverage the work done on upstream 5.x and use the same here on 5.4 kernel. This helps to align the downstream code. Any changes that happen because of upstream review can be cherry picked here. If we plan for any downstream changes, upstream patch needs to be pushed to keep the code in sync. As of today current snapshot is pulled from v3 of AHUB series, http://patchwork.ozlabs.org/project/linux-tegra/list/?series=159664 Above series was worked on later versions of linux-next and hence following are the changes required for porting back on 5.4 * tegra_pcm_new() and tegra_pcm_free() are exposed from tegra_pcm.c and component driver callbacks use these. * Callback functions required for snd_pcm_ops in component driver are implemented by tegra_pcm.c * With this ADMAIF driver need not register platform device with ASoC core. For components (AHUB, ADMAIF, I2S, DMIC and DSPK) the downsream code differs in few aspects from the code that was pushed for v3. Some of them are listed below. * I2S driver in downstream implements startup()/shutdown() calls for DAI, which does some setup related to pinconfig and regulators. The same is true for DMIC and DSPK drivers as well. * Downstream ADMAIF drivers makes bandwidth requests in startup/shutdown() calls and has helper function for dumping registers. It also has additional DAI interfaces which are used for ADSP audio. * Downstream AHUB driver has DAI interfaces for connecting to all other modules. These differences will be cherry-picked as and when it is necessary. Bug 2845498 Change-Id: Id374967ecae26f6b7334a959fb23308d383c15f2 Signed-off-by: Sameer Pujar <spujar@nvidia.com>
133 lines
4.1 KiB
C
133 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_i2s.h - Definitions for Tegra210 I2S driver
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*
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* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA210_I2S_H__
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#define __TEGRA210_I2S_H__
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/* Register offsets from I2S*_BASE */
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#define TEGRA210_I2S_RX_ENABLE 0x0
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#define TEGRA210_I2S_RX_SOFT_RESET 0x4
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#define TEGRA210_I2S_RX_STATUS 0x0c
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#define TEGRA210_I2S_RX_INT_STATUS 0x10
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#define TEGRA210_I2S_RX_INT_MASK 0x14
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#define TEGRA210_I2S_RX_INT_SET 0x18
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#define TEGRA210_I2S_RX_INT_CLEAR 0x1c
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#define TEGRA210_I2S_RX_CIF_CTRL 0x20
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#define TEGRA210_I2S_RX_CTRL 0x24
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#define TEGRA210_I2S_RX_SLOT_CTRL 0x28
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#define TEGRA210_I2S_RX_CLK_TRIM 0x2c
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#define TEGRA210_I2S_RX_CYA 0x30
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#define TEGRA210_I2S_RX_CIF_FIFO_STATUS 0x34
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#define TEGRA210_I2S_TX_ENABLE 0x40
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#define TEGRA210_I2S_TX_SOFT_RESET 0x44
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#define TEGRA210_I2S_TX_STATUS 0x4c
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#define TEGRA210_I2S_TX_INT_STATUS 0x50
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#define TEGRA210_I2S_TX_INT_MASK 0x54
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#define TEGRA210_I2S_TX_INT_SET 0x58
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#define TEGRA210_I2S_TX_INT_CLEAR 0x5c
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#define TEGRA210_I2S_TX_CIF_CTRL 0x60
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#define TEGRA210_I2S_TX_CTRL 0x64
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#define TEGRA210_I2S_TX_SLOT_CTRL 0x68
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#define TEGRA210_I2S_TX_CLK_TRIM 0x6c
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#define TEGRA210_I2S_TX_CYA 0x70
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#define TEGRA210_I2S_TX_CIF_FIFO_STATUS 0x74
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#define TEGRA210_I2S_ENABLE 0x80
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#define TEGRA210_I2S_SOFT_RESET 0x84
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#define TEGRA210_I2S_CG 0x88
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#define TEGRA210_I2S_STATUS 0x8c
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#define TEGRA210_I2S_INT_STATUS 0x90
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#define TEGRA210_I2S_CTRL 0xa0
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#define TEGRA210_I2S_TIMING 0xa4
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#define TEGRA210_I2S_SLOT_CTRL 0xa8
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#define TEGRA210_I2S_CLK_TRIM 0xac
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#define TEGRA210_I2S_CYA 0xb0
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/* Bit fields, shifts and masks */
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#define I2S_DATA_SHIFT 8
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#define I2S_CTRL_DATA_OFFSET_MASK (0x7ff << I2S_DATA_SHIFT)
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#define I2S_EN_SHIFT 0
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#define I2S_EN_MASK BIT(I2S_EN_SHIFT)
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#define I2S_EN BIT(I2S_EN_SHIFT)
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#define I2S_FSYNC_WIDTH_SHIFT 24
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#define I2S_CTRL_FSYNC_WIDTH_MASK (0xff << I2S_FSYNC_WIDTH_SHIFT)
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#define I2S_POS_EDGE 0
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#define I2S_NEG_EDGE 1
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#define I2S_EDGE_SHIFT 20
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#define I2S_CTRL_EDGE_CTRL_MASK BIT(I2S_EDGE_SHIFT)
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#define I2S_CTRL_EDGE_CTRL_POS_EDGE (I2S_POS_EDGE << I2S_EDGE_SHIFT)
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#define I2S_CTRL_EDGE_CTRL_NEG_EDGE (I2S_NEG_EDGE << I2S_EDGE_SHIFT)
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#define I2S_FMT_LRCK 0
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#define I2S_FMT_FSYNC 1
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#define I2S_FMT_SHIFT 12
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#define I2S_CTRL_FRAME_FMT_MASK (7 << I2S_FMT_SHIFT)
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#define I2S_CTRL_FRAME_FMT_LRCK_MODE (I2S_FMT_LRCK << I2S_FMT_SHIFT)
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#define I2S_CTRL_FRAME_FMT_FSYNC_MODE (I2S_FMT_FSYNC << I2S_FMT_SHIFT)
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#define I2S_CTRL_MASTER_EN_SHIFT 10
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#define I2S_CTRL_MASTER_EN_MASK BIT(I2S_CTRL_MASTER_EN_SHIFT)
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#define I2S_CTRL_MASTER_EN BIT(I2S_CTRL_MASTER_EN_SHIFT)
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#define I2S_CTRL_LRCK_POL_SHIFT 9
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#define I2S_CTRL_LRCK_POL_MASK BIT(I2S_CTRL_LRCK_POL_SHIFT)
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#define I2S_CTRL_LRCK_POL_LOW (0 << I2S_CTRL_LRCK_POL_SHIFT)
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#define I2S_CTRL_LRCK_POL_HIGH BIT(I2S_CTRL_LRCK_POL_SHIFT)
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#define I2S_CTRL_LPBK_SHIFT 8
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#define I2S_CTRL_LPBK_MASK BIT(I2S_CTRL_LPBK_SHIFT)
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#define I2S_CTRL_LPBK_EN BIT(I2S_CTRL_LPBK_SHIFT)
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#define I2S_BITS_8 1
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#define I2S_BITS_16 3
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#define I2S_BITS_32 7
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#define I2S_CTRL_BIT_SIZE_MASK 0x7
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#define I2S_TIMING_CH_BIT_CNT_MASK 0x7ff
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#define I2S_TIMING_CH_BIT_CNT_SHIFT 0
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#define I2S_SOFT_RESET_SHIFT 0
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#define I2S_SOFT_RESET_MASK BIT(I2S_SOFT_RESET_SHIFT)
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#define I2S_SOFT_RESET_EN BIT(I2S_SOFT_RESET_SHIFT)
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#define I2S_RX_FIFO_DEPTH 64
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#define DEFAULT_I2S_RX_FIFO_THRESHOLD 3
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#define DEFAULT_I2S_SLOT_MASK 0xffff
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enum tegra210_i2s_path {
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I2S_RX_PATH,
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I2S_TX_PATH,
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I2S_PATHS,
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};
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struct tegra210_i2s {
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struct clk *clk_i2s;
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struct clk *clk_sync_input;
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struct regmap *regmap;
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unsigned int stereo_to_mono[I2S_PATHS];
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unsigned int mono_to_stereo[I2S_PATHS];
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unsigned int audio_ch_override[I2S_PATHS];
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unsigned int audio_fmt_override[I2S_PATHS];
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/* Client overrides are common for TX and RX paths */
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unsigned int client_ch_override;
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unsigned int client_fmt_override;
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unsigned int srate_override;
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unsigned int dai_fmt;
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unsigned int fsync_width;
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unsigned int bclk_ratio;
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unsigned int tx_mask;
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unsigned int rx_mask;
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unsigned int rx_fifo_th;
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bool loopback;
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};
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#endif
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