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git://nv-tegra.nvidia.com/linux-nv-oot.git
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685eb2c8d2
Add host1x05 version and fill in the h/w details in host1x05_info Add all the hardware accessors for T186 (channel, sync, uclass accessors) Add hardware support files for host1x channel, syncpoints, cdma, pushbuffer, interrupt, and debug support Keep gather filter disabled Things working with this : - cdma operations - basic channel job submit path - syncpoint support - syncpoint interrupt mechanism - debug dump With this support, below tests pass for VIC client $nvrm_channel channel_Basic $nvrm_channel --module=vic Bug 1704301 Change-Id: I7d97560cb1e3a57733fa0853936b0783c71b7060 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1021434 GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
129 lines
3.4 KiB
C
129 lines
3.4 KiB
C
/*
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* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __HOST1X_HOST1X05_HARDWARE_H
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#define __HOST1X_HOST1X05_HARDWARE_H
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include "hw_host1x05_channel.h"
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#include "hw_host1x05_sync.h"
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#include "hw_host1x05_uclass.h"
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static inline u32 host1x_class_host_wait_syncpt(
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unsigned indx, unsigned threshold)
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{
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return host1x_uclass_wait_syncpt_indx_f(indx)
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| host1x_uclass_wait_syncpt_thresh_f(threshold);
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}
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static inline u32 host1x_class_host_load_syncpt_base(
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unsigned indx, unsigned threshold)
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{
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return host1x_uclass_load_syncpt_base_base_indx_f(indx)
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| host1x_uclass_load_syncpt_base_value_f(threshold);
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}
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static inline u32 host1x_class_host_wait_syncpt_base(
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unsigned indx, unsigned base_indx, unsigned offset)
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{
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return host1x_uclass_wait_syncpt_base_indx_f(indx)
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| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
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| host1x_uclass_wait_syncpt_base_offset_f(offset);
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}
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static inline u32 host1x_class_host_incr_syncpt_base(
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unsigned base_indx, unsigned offset)
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{
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return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
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| host1x_uclass_incr_syncpt_base_offset_f(offset);
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}
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static inline u32 host1x_class_host_incr_syncpt(
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unsigned cond, unsigned indx)
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{
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return host1x_uclass_incr_syncpt_cond_f(cond)
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| host1x_uclass_incr_syncpt_indx_f(indx);
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}
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/* cdma opcodes */
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static inline u32 host1x_opcode_setclass(
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unsigned class_id, unsigned offset, unsigned mask)
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{
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return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
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}
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static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
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{
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return (1 << 28) | (offset << 16) | count;
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}
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static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
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{
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return (2 << 28) | (offset << 16) | count;
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}
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static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
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{
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return (3 << 28) | (offset << 16) | mask;
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}
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static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
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{
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return (4 << 28) | (offset << 16) | value;
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}
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static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
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{
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return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
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host1x_class_host_incr_syncpt(cond, indx));
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}
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static inline u32 host1x_opcode_restart(unsigned address)
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{
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return (5 << 28) | (address >> 4);
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}
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static inline u32 host1x_opcode_gather(unsigned count)
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{
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return (6 << 28) | count;
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}
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static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
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{
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return (6 << 28) | (offset << 16) | BIT(15) | count;
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}
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static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
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{
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return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
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}
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static inline u32 host1x_opcode_acquire_mlock(unsigned id)
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{
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return (14 << 28) | id;
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}
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static inline u32 host1x_opcode_release_mlock(unsigned id)
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{
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return (14 << 28) | (1 << 24) | id;
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}
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#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
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#endif
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