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git://nv-tegra.nvidia.com/linux-nv-oot.git
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685eb2c8d2
Add host1x05 version and fill in the h/w details in host1x05_info Add all the hardware accessors for T186 (channel, sync, uclass accessors) Add hardware support files for host1x channel, syncpoints, cdma, pushbuffer, interrupt, and debug support Keep gather filter disabled Things working with this : - cdma operations - basic channel job submit path - syncpoint support - syncpoint interrupt mechanism - debug dump With this support, below tests pass for VIC client $nvrm_channel channel_Basic $nvrm_channel --module=vic Bug 1704301 Change-Id: I7d97560cb1e3a57733fa0853936b0783c71b7060 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1021434 GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
322 lines
9.6 KiB
C
322 lines
9.6 KiB
C
/*
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* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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* Function naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef HOST1X_HW_HOST1X05_SYNC_H
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#define HOST1X_HW_HOST1X05_SYNC_H
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#define REGISTER_STRIDE 4
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static inline u32 host1x_sync_intstatus_r(void)
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{
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return 0x1c;
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}
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#define HOST1X_SYNC_INTSTATUS \
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host1x_sync_intstatus_r()
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static inline u32 host1x_sync_intmask_r(void)
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{
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return 0x30;
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}
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#define HOST1X_SYNC_INTMASK \
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host1x_sync_intmask_r()
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static inline u32 host1x_sync_intc0mask_r(void)
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{
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return 0x4;
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}
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#define HOST1X_SYNC_INTC0MASK \
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host1x_sync_intc0mask_r()
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static inline u32 host1x_sync_intgmask_r(void)
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{
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return 0x44;
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}
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#define HOST1X_SYNC_INTGMASK \
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host1x_sync_intgmask_r()
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static inline u32 host1x_sync_syncpt_intgmask_r(void)
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{
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return 0x50;
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}
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#define HOST1X_SYNC_SYNCPT_INTGMASK \
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host1x_sync_syncpt_intgmask_r()
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static inline u32 host1x_sync_intstatus_ip_read_int_v(u32 r)
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{
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return (r >> 0) & 0x1;
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}
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#define HOST1X_SYNC_INTSTATUS_IP_READ_INT_V(r) \
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host1x_sync_intstatus_ip_read_int_v(r)
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static inline u32 host1x_sync_intstatus_ip_write_int_v(u32 r)
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{
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return (r >> 1) & 0x1;
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}
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#define HOST1X_SYNC_INTSTATUS_IP_WRITE_INT_V(r) \
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host1x_sync_intstatus_ip_write_int_v(r)
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static inline u32 host1x_sync_intstatus_illegal_pb_access_v(u32 r)
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{
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return (r >> 28) & 0x1;
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}
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#define HOST1X_SYNC_INTSTATUS_ILLEGAL_PB_ACCESS_V(r) \
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host1x_sync_intstatus_illegal_pb_access_v(r)
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static inline u32 host1x_sync_illegal_syncpt_access_frm_pb_r(void)
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{
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return 0x2270;
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}
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#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_PB \
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host1x_sync_illegal_syncpt_access_frm_pb_r()
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static inline u32 host1x_sync_illegal_syncpt_access_frm_pb_syncpt_v(u32 r)
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{
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return (r >> 16) & 0x3ff;
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}
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#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_PB_SYNCPT_V(r) \
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host1x_sync_illegal_syncpt_access_frm_pb_syncpt_v(r)
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static inline u32 host1x_sync_illegal_syncpt_access_frm_pb_ch_v(u32 r)
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{
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return (r >> 10) & 0x3f;
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}
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#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_PB_CH_V(r) \
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host1x_sync_illegal_syncpt_access_frm_pb_ch_v(r)
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static inline u32 host1x_sync_intstatus_illegal_client_access_v(u32 r)
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{
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return (r >> 30) & 0x1;
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}
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#define HOST1X_SYNC_INTSTATUS_ILLEGAL_CLIENT_ACCESS_V(r) \
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host1x_sync_intstatus_illegal_client_access_v(r)
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static inline u32 host1x_sync_illegal_syncpt_access_frm_client_r(void)
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{
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return 0x2268;
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}
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#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_CLIENT \
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host1x_sync_illegal_syncpt_access_frm_client_r()
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static inline u32 host1x_sync_illegal_syncpt_access_frm_client_syncpt_v(u32 r)
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{
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return (r >> 16) & 0x3ff;
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}
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#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_CLIENT_SYNCPT_V(r) \
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host1x_sync_illegal_syncpt_access_frm_client_syncpt_v(r)
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static inline u32 host1x_sync_illegal_syncpt_access_frm_client_ch_v(u32 r)
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{
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return (r >> 10) & 0x3f;
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}
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#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_CLIENT_CH_V(r) \
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host1x_sync_illegal_syncpt_access_frm_client_ch_v(r)
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static inline u32 host1x_sync_syncpt_r(unsigned int id)
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{
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return 0x18080 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT(id) \
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host1x_sync_syncpt_r(id)
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static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id)
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{
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return 0x16464 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \
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host1x_sync_syncpt_thresh_cpu0_int_status_r(id)
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static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id)
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{
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return 0x16590 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \
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host1x_sync_syncpt_thresh_int_disable_r(id)
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static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id)
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{
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return 0x1652c + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \
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host1x_sync_syncpt_thresh_int_enable_cpu0_r(id)
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static inline u32 host1x_sync_cf_setup_r(unsigned int channel)
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{
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return 0x2588 + channel * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_CF_SETUP(channel) \
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host1x_sync_cf_setup_r(channel)
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static inline u32 host1x_sync_cf_setup_base_v(u32 r)
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{
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return (r >> 0) & 0xfff;
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}
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#define HOST1X_SYNC_CF_SETUP_BASE_V(r) \
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host1x_sync_cf_setup_base_v(r)
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static inline u32 host1x_sync_cf_setup_limit_v(u32 r)
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{
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return (r >> 16) & 0xfff;
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}
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#define HOST1X_SYNC_CF_SETUP_LIMIT_V(r) \
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host1x_sync_cf_setup_limit_v(r)
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static inline u32 host1x_sync_cmdproc_stop_r(void)
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{
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return 0x48;
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}
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#define HOST1X_SYNC_CMDPROC_STOP \
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host1x_sync_cmdproc_stop_r()
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static inline u32 host1x_sync_ch_teardown_r(void)
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{
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return 0x4c;
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}
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#define HOST1X_SYNC_CH_TEARDOWN \
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host1x_sync_ch_teardown_r()
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static inline u32 host1x_sync_usec_clk_r(void)
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{
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return 0x2244;
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}
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#define HOST1X_SYNC_USEC_CLK \
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host1x_sync_usec_clk_r()
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static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void)
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{
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return 0x2248;
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}
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#define HOST1X_SYNC_CTXSW_TIMEOUT_CFG \
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host1x_sync_ctxsw_timeout_cfg_r()
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static inline u32 host1x_sync_ip_busy_timeout_r(void)
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{
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return 0x2250;
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}
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#define HOST1X_SYNC_IP_BUSY_TIMEOUT \
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host1x_sync_ip_busy_timeout_r()
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static inline u32 host1x_sync_ip_read_timeout_addr_r(void)
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{
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return 0x2254;
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}
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#define HOST1X_SYNC_IP_READ_TIMEOUT_ADDR \
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host1x_sync_ip_read_timeout_addr_r()
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static inline u32 host1x_sync_ip_write_timeout_addr_r(void)
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{
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return 0x225c;
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}
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#define HOST1X_SYNC_IP_WRITE_TIMEOUT_ADDR \
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host1x_sync_ip_write_timeout_addr_r()
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static inline u32 host1x_sync_syncpt_int_thresh_r(unsigned int id)
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{
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return 0x18a00 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_INT_THRESH(id) \
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host1x_sync_syncpt_int_thresh_r(id)
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static inline u32 host1x_sync_syncpt_base_r(unsigned int id)
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{
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return 0x18000 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_BASE(id) \
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host1x_sync_syncpt_base_r(id)
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static inline u32 host1x_sync_syncpt_cpu_incr_r(unsigned int id)
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{
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return 0x16400 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_SYNCPT_CPU_INCR(id) \
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host1x_sync_syncpt_cpu_incr_r(id)
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static inline u32 host1x_sync_cfpeek_ctrl_r(void)
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{
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return 0x233c;
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}
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#define HOST1X_SYNC_CFPEEK_CTRL \
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host1x_sync_cfpeek_ctrl_r()
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static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v)
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{
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return (v & 0xfff) << 0;
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}
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#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \
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host1x_sync_cfpeek_ctrl_addr_f(v)
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static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v)
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{
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return (v & 0x3f) << 16;
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}
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#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \
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host1x_sync_cfpeek_ctrl_channr_f(v)
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static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v)
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{
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return (v & 0x1) << 31;
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}
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#define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \
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host1x_sync_cfpeek_ctrl_ena_f(v)
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static inline u32 host1x_sync_cfpeek_read_r(void)
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{
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return 0x2340;
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}
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#define HOST1X_SYNC_CFPEEK_READ \
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host1x_sync_cfpeek_read_r()
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static inline u32 host1x_sync_cfpeek_ptrs_r(void)
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{
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return 0x2344;
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}
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#define HOST1X_SYNC_CFPEEK_PTRS \
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host1x_sync_cfpeek_ptrs_r()
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static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r)
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{
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return (r >> 0) & 0xfff;
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}
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#define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(r) \
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host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(r)
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static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r)
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{
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return (r >> 16) & 0xfff;
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}
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#define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(r) \
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host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(r)
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static inline u32 host1x_sync_common_mlock_r(unsigned long id)
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{
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return 0x2030 + id * REGISTER_STRIDE;
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}
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#define HOST1X_SYNC_COMMON_MLOCK \
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host1x_sync_common_mlock_r()
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static inline u32 host1x_sync_common_mlock_ch_v(u32 r)
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{
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return (r >> 2) & 0x3f;
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}
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#define HOST1X_SYNC_COMMON_MLOCK_CH_V(r) \
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host1x_sync_common_mlock_ch_v(r)
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static inline u32 host1x_sync_common_mlock_locked_v(u32 r)
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{
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return (r >> 0) & 0x1;
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}
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#define HOST1X_SYNC_COMMON_MLOCK_LOCKED_V(r) \
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host1x_sync_common_mlock_locked_v(r)
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static inline u32 host1x_thost_common_icg_en_override_0_r(void)
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{
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return 0x2aa8;
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}
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#define HOST1X_THOST_COMMON_ICG_EN_OVERRIDE_0 \
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host1x_thost_common_icg_en_override_0_r()
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#endif
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