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Add host1x05 version and fill in the h/w details in host1x05_info Add all the hardware accessors for T186 (channel, sync, uclass accessors) Add hardware support files for host1x channel, syncpoints, cdma, pushbuffer, interrupt, and debug support Keep gather filter disabled Things working with this : - cdma operations - basic channel job submit path - syncpoint support - syncpoint interrupt mechanism - debug dump With this support, below tests pass for VIC client $nvrm_channel channel_Basic $nvrm_channel --module=vic Bug 1704301 Change-Id: I7d97560cb1e3a57733fa0853936b0783c71b7060 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1021434 GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
127 lines
3.3 KiB
C
127 lines
3.3 KiB
C
/*
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* Tegra host1x Syncpoints
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*
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* Copyright (c) 2016, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/io.h>
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#include "dev.h"
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#include "syncpt.h"
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/*
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* Write the current syncpoint value back to hw.
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*/
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static void syncpt_restore(struct host1x_syncpt *sp)
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{
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struct host1x *host = sp->host;
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int min = host1x_syncpt_read_min(sp);
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host1x_sync_writel(host, min, HOST1X_SYNC_SYNCPT(sp->id));
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}
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/*
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* Write the current waitbase value back to hw.
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*/
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static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
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{
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struct host1x *host = sp->host;
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host1x_sync_writel(host, sp->base_val,
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HOST1X_SYNC_SYNCPT_BASE(sp->id));
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}
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/*
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* Read waitbase value from hw.
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*/
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static void syncpt_read_wait_base(struct host1x_syncpt *sp)
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{
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struct host1x *host = sp->host;
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sp->base_val =
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host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(sp->id));
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}
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/*
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* Updates the last value read from hardware.
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*/
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static u32 syncpt_load(struct host1x_syncpt *sp)
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{
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struct host1x *host = sp->host;
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u32 old, live;
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/* Loop in case there's a race writing to min_val */
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do {
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old = host1x_syncpt_read_min(sp);
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live = host1x_sync_readl(host, HOST1X_SYNC_SYNCPT(sp->id));
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} while ((u32)atomic_cmpxchg(&sp->min_val, old, live) != old);
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if (!host1x_syncpt_check_max(sp, live))
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dev_err(host->dev, "%s failed: id=%u, min=%d, max=%d\n",
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__func__, sp->id, host1x_syncpt_read_min(sp),
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host1x_syncpt_read_max(sp));
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return live;
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}
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/*
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* Write a cpu syncpoint increment to the hardware, without touching
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* the cache.
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*/
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static int syncpt_cpu_incr(struct host1x_syncpt *sp)
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{
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struct host1x *host = sp->host;
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u32 reg_offset = sp->id / 32;
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if (!host1x_syncpt_client_managed(sp) &&
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host1x_syncpt_idle(sp))
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return -EINVAL;
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host1x_sync_writel(host, BIT_MASK(sp->id),
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HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset));
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wmb();
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return 0;
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}
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/* remove a wait pointed to by patch_addr */
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static int syncpt_patch_wait(struct host1x_syncpt *sp, void *patch_addr)
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{
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u32 override = host1x_class_host_wait_syncpt(
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HOST1X_SYNCPT_RESERVED, 0);
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*((u32 *)patch_addr) = override;
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return 0;
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}
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static void syncpt_get_mutex_owner(struct host1x_syncpt *sp,
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unsigned int mutex_id, bool *cpu, bool *ch,
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unsigned int *chid)
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{
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struct host1x *host = sp->host;
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u32 owner;
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owner = host1x_sync_readl(host, host1x_sync_common_mlock_r(mutex_id));
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*chid = HOST1X_SYNC_COMMON_MLOCK_CH_V(owner);
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*ch = HOST1X_SYNC_COMMON_MLOCK_LOCKED_V(owner);
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*cpu = false;
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}
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static const struct host1x_syncpt_ops host1x_syncpt_t186_ops = {
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.restore = syncpt_restore,
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.restore_wait_base = syncpt_restore_wait_base,
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.load_wait_base = syncpt_read_wait_base,
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.load = syncpt_load,
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.cpu_incr = syncpt_cpu_incr,
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.patch_wait = syncpt_patch_wait,
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.get_mutex_owner = syncpt_get_mutex_owner,
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};
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