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719434d072
Earlier hardcoded pll base rates were leading to fractional divider values for i2s multichannel config while deriving i2s bclk. Hence updated clock rates and logic for >2 channel configs for t186ref and higher boards such that the dynamic range between max plla and min plla is < 35 MHz. Also, if desired bclk is above limit, the case will be declared as not supported. Note that new facility will be used only in l4t machine driver. Bug 200702569 Change-Id: I83aba425f6dde30a1f29f85b16a1bbbebba14198 Signed-off-by: Asha Talambedu <atalambedu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2491744 (cherry picked from commit e0fe51d5e7ced073eb618e19836f88a023f70bdc) Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.10/+/2613507 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Mohan Kumar D <mkumard@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra_asoc_utils.h - Definitions for Tegra DAS driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (c) 2010,2012-2021, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __TEGRA_ASOC_UTILS_H__
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#define __TEGRA_ASOC_UTILS_H__
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struct clk;
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struct device;
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enum tegra_asoc_utils_soc {
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TEGRA_ASOC_UTILS_SOC_TEGRA20,
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TEGRA_ASOC_UTILS_SOC_TEGRA30,
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TEGRA_ASOC_UTILS_SOC_TEGRA114,
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TEGRA_ASOC_UTILS_SOC_TEGRA124,
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TEGRA_ASOC_UTILS_SOC_TEGRA210,
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TEGRA_ASOC_UTILS_SOC_TEGRA186,
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TEGRA_ASOC_UTILS_SOC_TEGRA194,
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TEGRA_ASOC_UTILS_SOC_TEGRA234,
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};
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struct tegra_asoc_utils_data {
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struct device *dev;
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enum tegra_asoc_utils_soc soc;
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struct clk *clk_pll_a;
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struct clk *clk_pll_a_out0;
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struct clk *clk_cdev1;
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int set_baseclock;
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int set_mclk;
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unsigned int set_pll_out;
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unsigned int *pll_base_rate;
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unsigned int mclk_fs;
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bool fixed_pll;
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};
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int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
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int mclk);
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int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data);
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int tegra_asoc_utils_set_tegra210_rate(struct tegra_asoc_utils_data *data,
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unsigned int sample_rate,
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unsigned int channels,
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unsigned int sample_size);
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int tegra_asoc_utils_clk_enable(struct tegra_asoc_utils_data *data);
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void tegra_asoc_utils_clk_disable(struct tegra_asoc_utils_data *data);
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int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
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struct device *dev);
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#endif
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