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0e6d4c804f
- Ordering between message/data and host1x syncpoints is not enforced strictly. - Out of the possible WARs, implement dummy PCIe Read between data/message write and notifications towards peer / remote post-fences. - WAR: (IPC/messaging mode)For any UMD produced data towards peer, before notification is triggered, issue a dummy PCIe read via CPU. - WAR: (streaming mode)DMA flush-ranges(data), wait for DMA interrupt, when success issue dummy PCIe reads via CPU on remote post-fences + issue CPU PCIe writes on each remote post-fence. To achieve this, CPU map every imported sync object. NVIPC-974 Change-Id: Id6711d372c0a35e13e399ffbbcd8efcabf147c56 Signed-off-by: Arihant Jejani <ajejani@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2912894 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Janardhan Reddy A <jreddya@nvidia.com> Reviewed-by: Vipin Kumar <vipink@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>