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git://nv-tegra.nvidia.com/linux-nv-oot.git
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1b6da7e345
To support interrupt-driven DFS, we need to enable actmon interrupt for OFA. Bug 4310958 Signed-off-by: Johnny Liu <johnliu@nvidia.com> Change-Id: I0615ad4b28bb6d4bc6cd666eb354901f294f6173 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3001885 Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
96 lines
2.7 KiB
C
96 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Tegra host1x General Interrupt Management
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*
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* Copyright (C) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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#include <linux/interrupt.h>
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#include "../dev.h"
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static irqreturn_t host1x_general_isr(int irq, void *dev_id)
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{
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struct host1x *host = dev_id;
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unsigned long status;
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status = host1x_common_readl(host, HOST1X_COMMON_THOST_INTRSTATUS);
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if (status & HOST1X_COMMON_THOST_INTRSTATUS_NVENC_ACTMON_INTR)
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host1x_actmon_handle_interrupt(host, HOST1X_CLASS_NVENC);
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if (status & HOST1X_COMMON_THOST_INTRSTATUS_VIC_ACTMON_INTR)
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host1x_actmon_handle_interrupt(host, HOST1X_CLASS_VIC);
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if (status & HOST1X_COMMON_THOST_INTRSTATUS_NVDEC_ACTMON_INTR)
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host1x_actmon_handle_interrupt(host, HOST1X_CLASS_NVDEC);
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if (status & HOST1X_COMMON_THOST_INTRSTATUS_NVJPG_ACTMON_INTR)
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host1x_actmon_handle_interrupt(host, HOST1X_CLASS_NVJPG);
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if (status & HOST1X_COMMON_THOST_INTRSTATUS_NVJPG1_ACTMON_INTR)
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host1x_actmon_handle_interrupt(host, HOST1X_CLASS_NVJPG1);
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if (status & HOST1X_COMMON_THOST_INTRSTATUS_OFA_ACTMON_INTR)
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host1x_actmon_handle_interrupt(host, HOST1X_CLASS_OFA);
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host1x_common_writel(host, status, HOST1X_COMMON_THOST_INTRSTATUS);
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return IRQ_HANDLED;
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}
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static int host1x_intr_init_host_general(struct host1x *host)
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{
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int err;
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host1x_hw_intr_disable_all_general_intrs(host);
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err = devm_request_threaded_irq(host->dev,
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host->general_irq,
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NULL, host1x_general_isr,
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IRQF_ONESHOT, "host1x_general",
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host);
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if (err < 0) {
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devm_free_irq(host->dev, host->general_irq, host);
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return err;
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}
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return 0;
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}
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static void host1x_intr_enable_general_intrs(struct host1x *host)
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{
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if (!host->common_regs)
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return;
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/* Assign CPU0 for host1x general interrupts */
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host1x_common_writel(host, 0x1, HOST1X_COMMON_INTR_CPU0_MASK);
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/* Allow host1x general interrupts go to CPU0 only */
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host1x_common_writel(host, 0x1, HOST1X_COMMON_THOST_GLOBAL_INTRMASK);
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/* Enable host1x general interrupts */
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host1x_common_writel(host,
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HOST1X_COMMON_THOST_INTRMASK_NVENC_ACTMON(1) |
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HOST1X_COMMON_THOST_INTRMASK_VIC_ACTMON(1) |
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HOST1X_COMMON_THOST_INTRMASK_NVDEC_ACTMON(1) |
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HOST1X_COMMON_THOST_INTRMASK_NVJPG_ACTMON(1) |
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HOST1X_COMMON_THOST_INTRMASK_NVJPG1_ACTMON(1)|
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HOST1X_COMMON_THOST_INTRMASK_OFA_ACTMON(1),
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HOST1X_COMMON_THOST_INTRMASK);
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}
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static void host1x_intr_disable_all_general_intrs(struct host1x *host)
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{
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if (!host->common_regs)
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return;
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host1x_common_writel(host, 0x0, HOST1X_COMMON_THOST_INTRMASK);
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}
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static const struct host1x_intr_general_ops host1x_intr_general_ops = {
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.init_host_general = host1x_intr_init_host_general,
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.enable_general_intrs = host1x_intr_enable_general_intrs,
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.disable_all_general_intrs = host1x_intr_disable_all_general_intrs,
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};
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