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During PTP operation, abnormal interrupt handling could stall internal transactions, leading to delayed BAR register reads and PCIe completion timeout errors. This patch adjusts the PTP interrupt mechanism to eliminate the stall and reduce latency. Bug 4755448 Change-Id: Id7fa3fbcac33ba89b3635d86a15932ac95f7e4bd Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3446108 Reviewed-by: Brad Griffis <bgriffis@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Shobek Attupurath <sattupurath@nvidia.com>