mirror of
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283315b000
- Rename dce-os-device to dce-linux-device - dce-os-device.h header is specific to OS and is only intended to be internally used within OS. Similarly all it's exposed functions are OS specific only. - Therefore instead of having a common name for all OSs for this header file, make this header internal by including linux name to it's naming convention. - Similary rename dce_os_device struct to dce_linux_device and also rename corresponding functions from this header. JIRA TDS-16126 Change-Id: I74e2deb17f49065d242bd80d50c5a849b3dfa3a1 Signed-off-by: anupamg <anupamg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3256403 Reviewed-by: Arun Swain <arswain@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
632 lines
15 KiB
C
632 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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#include <dce.h>
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#include <dce-os-log.h>
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#include <dce-os-utils.h>
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#include <dce-linux-device.h>
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#define MAX_NO_ASTS 2
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#define MAX_AST_REGIONS 1
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#define MAX_AST_STRMCTLS 2
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#define AST_MASTER_ADDR_HI_BITS_SHIFT 32
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/**
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* dce_get_phys_stream_id - Gets the physical stream ID to be programmed from
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* platform data.
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : Stream ID Value
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*/
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static u8 dce_get_phys_stream_id(struct tegra_dce *d)
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{
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return pdata_from_dce_linux_device(d)->phys_stream_id;
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}
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/**
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* dce_get_fw_vm_index - Gets the VMIndex for the fw region to be
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* programmed from platform data.
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : VMIndex
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*/
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static u8 dce_get_fw_vm_index(struct tegra_dce *d)
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{
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return pdata_from_dce_linux_device(d)->fw_vmindex;
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}
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/**
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* dce_get_fw_carveout_id- Gets the carveout ID for the fw region to be
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* programmed from platform data.
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : Carveout Id
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*/
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static u8 dce_get_fw_carveout_id(struct tegra_dce *d)
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{
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return pdata_from_dce_linux_device(d)->fw_carveout_id;
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}
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/**
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* dce_is_physical_id_valid - Checks if the DCE can use physical stream ID.
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : True if SMMU is disabled.
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*/
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static bool dce_is_physical_id_valid(struct tegra_dce *d)
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{
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return pdata_from_dce_linux_device(d)->use_physical_id;
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}
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/**
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* dce_get_fw_dce_addr - Gets the 32bit address to be used for
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* loading the fw before being converted
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* by AST into a 40-bit address.
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : 32bit address
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*/
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static u32 dce_get_fw_dce_addr(struct tegra_dce *d)
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{
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return pdata_from_dce_linux_device(d)->fw_dce_addr;
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}
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/**
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* dce_config_ast0_control - programs the global
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* ast control register for AST0
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*
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* @d : Pointer to tegra_dce struct
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*
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* Return : Void
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*/
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static void dce_config_ast0_control(struct tegra_dce *d)
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{
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u32 val;
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u32 def_physical;
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u32 phy_stream_id = dce_get_phys_stream_id(d) <<
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ast_ast0_control_physstreamid_shift_v();
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if (dce_is_physical_id_valid(d))
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def_physical = 1 <<
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ast_ast0_control_carveoutlock_defphysical_shift_v();
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else
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def_physical = 0 <<
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ast_ast0_control_carveoutlock_defphysical_shift_v();
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val = phy_stream_id | ast_ast0_control_carveoutlock_false_f()
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| def_physical | ast_ast0_control_matcherrctl_decerr_f()
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| ast_ast0_control_lock_false_f();
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dce_os_writel(d, ast_ast0_control_r(), val);
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}
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/**
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* dce_config_ast1_control - programs the global
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* ast control register for AST1
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*
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* @d : Pointer to tegra_dce struct
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*
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* Return : Void
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*/
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static void dce_config_ast1_control(struct tegra_dce *d)
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{
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u32 val;
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u32 def_physical;
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u32 phy_stream_id = dce_get_phys_stream_id(d) <<
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ast_ast1_control_physstreamid_shift_v();
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if (dce_is_physical_id_valid(d))
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def_physical = 1 <<
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ast_ast1_control_carveoutlock_defphysical_shift_v();
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else
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def_physical = 0 <<
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ast_ast1_control_carveoutlock_defphysical_shift_v();
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val = phy_stream_id | ast_ast1_control_carveoutlock_false_f()
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| def_physical | ast_ast1_control_matcherrctl_decerr_f()
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| ast_ast1_control_lock_false_f();
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dce_os_writel(d, ast_ast1_control_r(), val);
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}
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/**
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* ast_ctl_fn is an array of read-only pointers
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* to a function returning void.
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*
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* Contains all the functions to program the global
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* ast control registers defined above.
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*/
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static void (*const ast_ctl_fn[MAX_NO_ASTS])(struct tegra_dce *d) = {
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dce_config_ast0_control,
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dce_config_ast1_control,
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};
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/**
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* dce_cfg_ast0_streamid_ctl_0 - programs the ast streamid
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* control register for AST0 and Control0
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*
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* @d : Pointer to tegra_dce struct
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*
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* Return : Void
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*/
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static void dce_cfg_ast0_streamid_ctl_0(struct tegra_dce *d)
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{
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u32 stream_id_en;
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u32 dce_stream_id = dce_os_get_dce_stream_id(d);
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if (dce_is_physical_id_valid(d))
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stream_id_en = ast_ast0_streamid_ctl_0_enable_disable_f();
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else
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stream_id_en = ast_ast0_streamid_ctl_0_enable_enable_f();
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dce_os_writel(d, ast_ast0_streamid_ctl_0_r(),
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(dce_stream_id << ast_ast0_streamid_ctl_0_streamid_shift_v()) |
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stream_id_en);
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}
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/**
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* dce_cfg_ast0_streamid_ctl_1 - programs the ast streamid
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* control register for AST0 and Control1
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*
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* @d : Pointer to tegra_dce struct
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*
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* Return : Void
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*/
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static void dce_cfg_ast0_streamid_ctl_1(struct tegra_dce *d)
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{
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u32 stream_id_en;
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u32 dce_stream_id = dce_os_get_dce_stream_id(d);
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if (dce_is_physical_id_valid(d))
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stream_id_en = ast_ast0_streamid_ctl_1_enable_disable_f();
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else
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stream_id_en = ast_ast0_streamid_ctl_1_enable_enable_f();
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dce_os_writel(d, ast_ast0_streamid_ctl_1_r(), (dce_stream_id <<
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ast_ast0_streamid_ctl_1_streamid_shift_v()) |
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stream_id_en);
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}
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/**
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* dce_cfg_ast1_streamid_ctl_0 - programs the ast streamid
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* control register for AST1 and Control0
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*
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* @d : Pointer to tegra_dce struct
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*
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* Return : Void
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*/
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static void dce_cfg_ast1_streamid_ctl_0(struct tegra_dce *d)
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{
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u32 stream_id_en;
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u32 dce_stream_id = dce_os_get_dce_stream_id(d);
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if (dce_is_physical_id_valid(d))
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stream_id_en = ast_ast1_streamid_ctl_0_enable_disable_f();
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else
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stream_id_en = ast_ast1_streamid_ctl_0_enable_enable_f();
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dce_os_writel(d, ast_ast1_streamid_ctl_0_r(),
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(dce_stream_id << ast_ast1_streamid_ctl_0_streamid_shift_v()) |
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stream_id_en);
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}
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/**
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* dce_cfg_ast1_streamid_ctl_1 - programs the ast streamid
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* control register for AST1 and Control1
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*
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* @d : Pointer to tegra_dce struct
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*
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* Return : Void
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*/
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static void dce_cfg_ast1_streamid_ctl_1(struct tegra_dce *d)
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{
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u32 stream_id_en;
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u32 dce_stream_id = dce_os_get_dce_stream_id(d);
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if (dce_is_physical_id_valid(d))
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stream_id_en = ast_ast1_streamid_ctl_1_enable_disable_f();
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else
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stream_id_en = ast_ast1_streamid_ctl_1_enable_enable_f();
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dce_os_writel(d, ast_ast1_streamid_ctl_1_r(),
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(dce_stream_id << ast_ast1_streamid_ctl_1_streamid_shift_v()) |
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stream_id_en);
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}
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/**
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* ast_strmidctl_fn is a 2D array of read-only pointers
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* to a function returning void.
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*
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* Contains all the functions to program the streamId
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* controls registers defined above for a given AST and Control ID
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*/
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static void (*const ast_strmidctl_fn[MAX_NO_ASTS][MAX_AST_STRMCTLS])
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(struct tegra_dce *d) = {
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{
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dce_cfg_ast0_streamid_ctl_0,
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dce_cfg_ast0_streamid_ctl_1,
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},
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{
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dce_cfg_ast1_streamid_ctl_0,
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dce_cfg_ast1_streamid_ctl_1,
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},
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};
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/**
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* dce_set_ast0_slave_addr_32_reg0 - programs the ast slave address
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* for AST0 and Region0
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*
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* @d : Pointer to tegra_dce sturct.
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* @addr : Address to be programmed.
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*
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* Return : Void
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*/
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static void dce_set_ast0_slave_addr_32_reg0(struct tegra_dce *d, u32 addr)
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{
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dce_os_writel(d, ast_ast0_region_0_slave_base_lo_r(),
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(addr | ast_ast0_region_0_slave_base_lo_enable_true_f()) &
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ast_ast1_region_0_slave_base_lo_write_mask_v());
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}
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/**
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* dce_set_ast1_slave_addr_32_reg0- programs the ast slave address
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* for AST1 and Region0
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*
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* @d : Pointer to tegra_dce sturct.
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* @addr : Address to be programmed.
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*
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* Return : Void
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*/
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static void dce_set_ast1_slave_addr_32_reg0(struct tegra_dce *d, u32 addr)
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{
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dce_os_writel(d, ast_ast1_region_0_slave_base_lo_r(),
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(addr | ast_ast1_region_0_slave_base_lo_enable_true_f()) &
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ast_ast1_region_0_slave_base_lo_write_mask_v());
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}
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/**
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* ast_slave_addr_fn is a 2D array of read-only pointers
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* to a function returning void.
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*
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* Contains all the functions to program the slave address and
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* other bits in salve address registers defined above for a
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* given AST and region.
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*/
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static void (*const ast_slave_addr_fn[MAX_NO_ASTS][MAX_AST_REGIONS])
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(struct tegra_dce *d, u32 addr) = {
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{
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dce_set_ast0_slave_addr_32_reg0,
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},
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{
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dce_set_ast1_slave_addr_32_reg0,
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},
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};
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/**
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* dce_set_ast0_master_addr_lo_reg0 - programs the lower 32 bits of ast
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* master address for AST0 and Region0
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*
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* @d : Pointer to tegra_dce sturct.
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* @addr : Address to be programmed.
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*
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* Return : Void
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*/
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static inline void
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dce_set_ast0_master_addr_lo_reg0(struct tegra_dce *d, u32 addr)
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{
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dce_os_writel(d, ast_ast0_region_0_master_base_lo_r(), addr);
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}
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/**
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* dce_set_ast1_master_addr_lo_reg0 - programs the lower 32 bits of ast
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* master address for AST1 and Region0
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*
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* @d : Pointer to tegra_dce sturct.
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* @addr : Address to be programmed.
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*
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* Return : Void
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*/
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static inline void
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dce_set_ast1_master_addr_lo_reg0(struct tegra_dce *d, u32 addr)
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{
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dce_os_writel(d, ast_ast1_region_0_master_base_lo_r(), addr);
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}
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/**
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* dce_set_ast1_master_addr_hi_reg0 - programs the high 32 bits of ast
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* master address for AST1 and Region0
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*
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* @d : Pointer to tegra_dce sturct.
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* @addr : Address to be programmed.
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*
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* Return : Void
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*/
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static inline void
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dce_set_ast1_master_addr_hi_reg0(struct tegra_dce *d, u32 addr)
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{
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dce_os_writel(d, ast_ast1_region_0_master_base_hi_r(), addr);
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}
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/**
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* dce_set_ast0_master_addr_hi_reg0 - programs the high 32 bits of ast
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* master address for AST0 and Region0
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*
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* @d : Pointer to tegra_dce sturct.
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* @addr : Address to be programmed.
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*
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* Return : Void
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*/
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static inline void
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dce_set_ast0_master_addr_hi_reg0(struct tegra_dce *d, u32 addr)
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{
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dce_os_writel(d, ast_ast0_region_0_master_base_hi_r(), addr);
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}
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/**
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* dce_set_ast0_master_addr_reg0 - programs the ast master address
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* for AST0 and Region0
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*
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* @d : Pointer to tegra_dce sturct.
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* @addr : Address to be programmed.
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*
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* Return : Void
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*/
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static void dce_set_ast0_master_addr_reg0(struct tegra_dce *d, u64 addr)
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{
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u32 ast_master_hi;
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u32 ast_master_lo;
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ast_master_lo = addr & ast_ast0_region_0_master_base_lo_write_mask_v();
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dce_set_ast0_master_addr_lo_reg0(d, ast_master_lo);
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ast_master_hi = addr >> AST_MASTER_ADDR_HI_BITS_SHIFT;
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dce_set_ast0_master_addr_hi_reg0(d, ast_master_hi);
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}
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/**
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* dce_set_ast1_master_addr_reg0 - programs the ast master address
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* for AST0 and Region0
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*
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* @d : Pointer to tegra_dce sturct.
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* @addr : Address to be programmed.
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*
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* Return : Void
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*/
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static void dce_set_ast1_master_addr_reg0(struct tegra_dce *d, u64 addr)
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{
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u32 ast_master_hi;
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u32 ast_master_lo;
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ast_master_lo = addr & ast_ast0_region_0_master_base_lo_write_mask_v();
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dce_set_ast1_master_addr_lo_reg0(d, ast_master_lo);
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ast_master_hi = addr >> AST_MASTER_ADDR_HI_BITS_SHIFT;
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dce_set_ast1_master_addr_hi_reg0(d, ast_master_hi);
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}
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/**
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* ast_master_addr_fn is a 2D array of read-only pointers
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* to a function returning void.
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*
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* Contains all the functions to program the master address registers
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* defined above for a given AST and region.
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*/
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static void (*const ast_master_addr_fn[MAX_NO_ASTS][MAX_AST_REGIONS])
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(struct tegra_dce *d, u64 addr) = {
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{
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dce_set_ast0_master_addr_reg0,
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},
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{
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dce_set_ast1_master_addr_reg0,
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},
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};
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/**
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* dce_get_fw_ast_reg_mask - Returns the size mask based on the fw size
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* for configuring AST region
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*
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* @d : Pointer to tegra_dce struct
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*
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* If size is 64K(0x10000), mask is 0xffff. If size is 2MB(0x200000), mask is
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* 0x1FFFFF.
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*
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* Ruturns 64 bit mask.
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*/
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static u64 dce_get_fw_ast_reg_mask(struct tegra_dce *d)
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{
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struct dce_firmware *fw = d->fw_data;
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return fw->size - 1UL;
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}
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/**
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* dce_ast_cfg_reg_mask_ast0_reg0 - sets the region mask based on the size
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* of the DRAM memory for AST0 and Region0.
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*
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* @d : pointer to tegra_dce struct
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*
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* Return : Void
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*/
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static void dce_ast_cfg_reg_mask_ast0_reg0(struct tegra_dce *d)
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{
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u64 size_mask = dce_get_fw_ast_reg_mask(d);
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u32 val = size_mask & ast_ast0_region_0_mask_lo_write_mask_v();
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dce_os_writel(d, ast_ast0_region_0_mask_lo_r(), val);
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}
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/**
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* dce_ast_cfg_reg_mask_ast1_reg0 - sets the region mask based on the size
|
|
* of the DRAM memory for AST1 and Region0.
|
|
*
|
|
* @d : pointer to tegra_dce struct
|
|
*
|
|
* Return : Void
|
|
*/
|
|
static void dce_ast_cfg_reg_mask_ast1_reg0(struct tegra_dce *d)
|
|
{
|
|
u64 size_mask = dce_get_fw_ast_reg_mask(d);
|
|
u32 val = size_mask & ast_ast1_region_0_mask_lo_write_mask_v();
|
|
|
|
dce_os_writel(d, ast_ast1_region_0_mask_lo_r(), val);
|
|
}
|
|
|
|
/**
|
|
* ast_mask_fn is a 2D array of read-only pointers
|
|
* to a function returning void.
|
|
*
|
|
* Contains all the functions to program the mask
|
|
* register bits for a given AST and region.
|
|
*/
|
|
static void (*const ast_mask_fn[MAX_NO_ASTS][MAX_AST_REGIONS])
|
|
(struct tegra_dce *d) = {
|
|
|
|
{
|
|
dce_ast_cfg_reg_mask_ast0_reg0,
|
|
},
|
|
{
|
|
dce_ast_cfg_reg_mask_ast1_reg0,
|
|
},
|
|
};
|
|
|
|
/**
|
|
* dce_ast_cfg_reg_control_ast0_reg0 - Configures the ast region control
|
|
* register for AST0 and Region0
|
|
*
|
|
* @d : Pointer to tegra_dce struct
|
|
*
|
|
* Return : Void
|
|
*/
|
|
static void dce_ast_cfg_reg_control_ast0_reg0(struct tegra_dce *d)
|
|
{
|
|
u32 vm_index;
|
|
u32 carveout_id;
|
|
u32 use_physical_id;
|
|
|
|
if (dce_is_physical_id_valid(d)) {
|
|
use_physical_id = 1 <<
|
|
ast_ast0_region_0_control_physical_shift_v();
|
|
vm_index = 0 <<
|
|
ast_ast0_region_0_control_vmindex_shift_v();
|
|
} else {
|
|
use_physical_id = 0 <<
|
|
ast_ast0_region_0_control_physical_shift_v();
|
|
vm_index = dce_get_fw_vm_index(d) <<
|
|
ast_ast0_region_0_control_vmindex_shift_v();
|
|
}
|
|
carveout_id = dce_get_fw_carveout_id(d) <<
|
|
ast_ast0_region_0_control_carveoutid_shift_v();
|
|
|
|
dce_os_writel(d, ast_ast0_region_0_control_r(),
|
|
use_physical_id | vm_index | carveout_id |
|
|
ast_ast0_region_0_control_snoop_enable_f());
|
|
}
|
|
|
|
/**
|
|
* dce_ast_cfg_reg_control_ast1_reg0 - Configures the ast region control
|
|
* register for AST1 and Region0
|
|
*
|
|
* @d : Pointer to tegra_dce struct
|
|
*
|
|
* Return : Void
|
|
*/
|
|
static void dce_ast_cfg_reg_control_ast1_reg0(struct tegra_dce *d)
|
|
{
|
|
u32 vm_index;
|
|
u32 carveout_id;
|
|
u32 use_physical_id;
|
|
|
|
if (dce_is_physical_id_valid(d)) {
|
|
use_physical_id = 1 <<
|
|
ast_ast1_region_0_control_physical_shift_v();
|
|
vm_index = 0 <<
|
|
ast_ast1_region_0_control_vmindex_shift_v();
|
|
} else {
|
|
use_physical_id = 0 <<
|
|
ast_ast1_region_0_control_physical_shift_v();
|
|
vm_index = dce_get_fw_vm_index(d) <<
|
|
ast_ast1_region_0_control_vmindex_shift_v();
|
|
}
|
|
|
|
carveout_id = dce_get_fw_carveout_id(d) <<
|
|
ast_ast1_region_0_control_carveoutid_shift_v();
|
|
|
|
|
|
dce_os_writel(d, ast_ast1_region_0_control_r(),
|
|
use_physical_id | vm_index | carveout_id |
|
|
ast_ast1_region_0_control_snoop_enable_f());
|
|
}
|
|
|
|
/**
|
|
* ast_reg_control_fn is a 2D array of read-only pointers
|
|
* to a function returning void.
|
|
*
|
|
* Contains all the functions to program the region control
|
|
* register bits given AST and region.
|
|
*/
|
|
static void (*const ast_reg_control_fn[MAX_NO_ASTS][MAX_AST_REGIONS])
|
|
(struct tegra_dce *d) = {
|
|
|
|
{
|
|
dce_ast_cfg_reg_control_ast0_reg0,
|
|
},
|
|
{
|
|
dce_ast_cfg_reg_control_ast1_reg0,
|
|
},
|
|
};
|
|
|
|
/**
|
|
* dce_config_ast - Configures the a AST region for initial loading of fw
|
|
* platform data.
|
|
*
|
|
* @d : Pointer to tegra_dce struct.
|
|
*
|
|
* Return : void
|
|
*/
|
|
void dce_config_ast(struct tegra_dce *d)
|
|
{
|
|
u8 i;
|
|
u8 j;
|
|
u32 slave_addr;
|
|
u64 master_addr;
|
|
|
|
d->boot_status |= DCE_AST_CONFIG_START;
|
|
slave_addr = dce_get_fw_dce_addr(d);
|
|
|
|
if (!d->fw_data) {
|
|
dce_os_err(d, "DCE_BOOT_FAILED: No fw_data present");
|
|
d->boot_status |= DCE_AST_CONFIG_FAILED;
|
|
return;
|
|
}
|
|
|
|
master_addr = d->fw_data->dma_handle;
|
|
|
|
for (i = 0; i < MAX_NO_ASTS; i++) {
|
|
ast_ctl_fn[i](d);
|
|
|
|
for (j = 0; j < MAX_AST_STRMCTLS; j++)
|
|
ast_strmidctl_fn[i][j](d);
|
|
|
|
for (j = 0; j < MAX_AST_REGIONS; j++) {
|
|
ast_mask_fn[i][j](d);
|
|
ast_reg_control_fn[i][j](d);
|
|
ast_master_addr_fn[i][j](d, master_addr);
|
|
ast_slave_addr_fn[i][j](d, slave_addr);
|
|
}
|
|
}
|
|
d->boot_status |= DCE_AST_CONFIG_DONE;
|
|
}
|