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95b8f25957
Add mfd driver for NVIDIA VRS sequencer. This device sequence the power rail required by SoCs. Bug 3583627 Change-Id: I774c286a61a5192478b9e8ceea839193c7cf6fe5 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2702275 GVS: Gerrit_Virtual_Submit
127 lines
4.7 KiB
C
127 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (C) 2022 NVIDIA CORPORATION. All rights reserved. */
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#ifndef _MFD_NVIDIA_VRS_PSEQ_H_
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#define _MFD_NVIDIA_VRS_PSEQ_H_
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#include <linux/types.h>
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/* Vendor ID */
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#define NVVRS_PSEQ_REG_VENDOR_ID 0x00
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#define NVVRS_PSEQ_REG_MODEL_REV 0x01
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/* Interrupts and Status registers */
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#define NVVRS_PSEQ_REG_INT_SRC1 0x10
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#define NVVRS_PSEQ_REG_INT_SRC2 0x11
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#define NVVRS_PSEQ_REG_INT_VENDOR 0x12
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#define NVVRS_PSEQ_REG_CTL_STAT 0x13
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#define NVVRS_PSEQ_REG_EN_STDR1 0x14
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#define NVVRS_PSEQ_REG_EN_STDR2 0x15
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#define NVVRS_PSEQ_REG_EN_STRD1 0x16
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#define NVVRS_PSEQ_REG_EN_STRD2 0x17
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#define NVVRS_PSEQ_REG_WDT_STAT 0x18
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#define NVVRS_PSEQ_REG_TEST_STAT 0x19
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#define NVVRS_PSEQ_REG_LAST_RST 0x1A
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/* Configuration Registers */
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#define NVVRS_PSEQ_REG_EN_ALT_F 0x20
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#define NVVRS_PSEQ_REG_AF_IN_OUT 0x21
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#define NVVRS_PSEQ_REG_EN_CFG1 0x22
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#define NVVRS_PSEQ_REG_EN_CFG2 0x23
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#define NVVRS_PSEQ_REG_CLK_CFG 0x24
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#define NVVRS_PSEQ_REG_GP_OUT 0x25
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#define NVVRS_PSEQ_REG_DEB_IN 0x26
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#define NVVRS_PSEQ_REG_LP_TTSHLD 0x27
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#define NVVRS_PSEQ_REG_CTL_1 0x28
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#define NVVRS_PSEQ_REG_CTL_2 0x29
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#define NVVRS_PSEQ_REG_TEST_CFG 0x2A
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#define NVVRS_PSEQ_REG_IEN_VENDOR 0x2B
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/* RTC */
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#define NVVRS_PSEQ_REG_RTC_T3 0x70
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#define NVVRS_PSEQ_REG_RTC_T2 0x71
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#define NVVRS_PSEQ_REG_RTC_T1 0x72
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#define NVVRS_PSEQ_REG_RTC_T0 0x73
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#define NVVRS_PSEQ_REG_RTC_A3 0x74
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#define NVVRS_PSEQ_REG_RTC_A2 0x75
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#define NVVRS_PSEQ_REG_RTC_A1 0x76
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#define NVVRS_PSEQ_REG_RTC_A0 0x77
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/* WDT */
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#define NVVRS_PSEQ_REG_WDT_CFG 0x80
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#define NVVRS_PSEQ_REG_WDT_CLOSE 0x81
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#define NVVRS_PSEQ_REG_WDT_OPEN 0x82
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#define NVVRS_PSEQ_REG_WDTKEY 0x83
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/* Interrupt Mask */
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#define NVVRS_PSEQ_INT_SRC1_RSTIRQ_MASK BIT(0)
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#define NVVRS_PSEQ_INT_SRC1_OSC_MASK BIT(1)
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#define NVVRS_PSEQ_INT_SRC1_EN_MASK BIT(2)
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#define NVVRS_PSEQ_INT_SRC1_RTC_MASK BIT(3)
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#define NVVRS_PSEQ_INT_SRC1_PEC_MASK BIT(4)
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#define NVVRS_PSEQ_INT_SRC1_WDT_MASK BIT(5)
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#define NVVRS_PSEQ_INT_SRC1_EM_PD_MASK BIT(6)
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#define NVVRS_PSEQ_INT_SRC1_INTERNAL_MASK BIT(7)
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#define NVVRS_PSEQ_INT_SRC2_PBSP_MASK BIT(0)
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#define NVVRS_PSEQ_INT_SRC2_ECC_DED_MASK BIT(1)
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#define NVVRS_PSEQ_INT_SRC2_TSD_MASK BIT(2)
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#define NVVRS_PSEQ_INT_SRC2_LDO_MASK BIT(3)
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#define NVVRS_PSEQ_INT_SRC2_BIST_MASK BIT(4)
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#define NVVRS_PSEQ_INT_SRC2_RT_CRC_MASK BIT(5)
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#define NVVRS_PSEQ_INT_SRC2_VENDOR_MASK BIT(7)
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#define NVVRS_PSEQ_INT_VENDOR0_MASK BIT(0)
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#define NVVRS_PSEQ_INT_VENDOR1_MASK BIT(1)
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#define NVVRS_PSEQ_INT_VENDOR2_MASK BIT(2)
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#define NVVRS_PSEQ_INT_VENDOR3_MASK BIT(3)
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#define NVVRS_PSEQ_INT_VENDOR4_MASK BIT(4)
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#define NVVRS_PSEQ_INT_VENDOR5_MASK BIT(5)
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#define NVVRS_PSEQ_INT_VENDOR6_MASK BIT(6)
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#define NVVRS_PSEQ_INT_VENDOR7_MASK BIT(7)
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/* Controller Register Mask */
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#define NVVRS_PSEQ_REG_CTL_1_FORCE_SHDN (BIT(0) | BIT(1))
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#define NVVRS_PSEQ_REG_CTL_1_FORCE_ACT BIT(2)
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#define NVVRS_PSEQ_REG_CTL_1_FORCE_INT BIT(3)
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#define NVVRS_PSEQ_REG_CTL_2_EN_PEC BIT(0)
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#define NVVRS_PSEQ_REG_CTL_2_REQ_PEC BIT(1)
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#define NVVRS_PSEQ_REG_CTL_2_RTC_PU BIT(2)
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#define NVVRS_PSEQ_REG_CTL_2_RTC_WAKE BIT(3)
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#define NVVRS_PSEQ_REG_CTL_2_RST_DLY 0xF0
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enum {
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NVVRS_PSEQ_INT_SRC1_RSTIRQ, /* Reset or Interrupt Pin Fault */
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NVVRS_PSEQ_INT_SRC1_OSC, /* Crystal Oscillator Fault */
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NVVRS_PSEQ_INT_SRC1_EN, /* Enable Output Pin Fault */
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NVVRS_PSEQ_INT_SRC1_RTC, /* RTC Alarm */
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NVVRS_PSEQ_INT_SRC1_PEC, /* Packet Error Checking */
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NVVRS_PSEQ_INT_SRC1_WDT, /* Watchdog Violation */
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NVVRS_PSEQ_INT_SRC1_EM_PD, /* Emergency Power Down */
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NVVRS_PSEQ_INT_SRC1_INTERNAL, /* Internal Fault*/
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NVVRS_PSEQ_INT_SRC2_PBSP, /* PWR_BTN Short Pulse Detection */
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NVVRS_PSEQ_INT_SRC2_ECC_DED, /* ECC Double-Error Detection */
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NVVRS_PSEQ_INT_SRC2_TSD, /* Thermal Shutdown */
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NVVRS_PSEQ_INT_SRC2_LDO, /* LDO Fault */
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NVVRS_PSEQ_INT_SRC2_BIST, /* Built-In Self Test Fault */
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NVVRS_PSEQ_INT_SRC2_RT_CRC, /* Runtime Register CRC Fault */
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NVVRS_PSEQ_INT_SRC2_VENDOR, /* Vendor Specific Internal Fault */
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NVVRS_PSEQ_INT_VENDOR0, /* Vendor Internal Fault Bit 0 */
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NVVRS_PSEQ_INT_VENDOR1, /* Vendor Internal Fault Bit 1 */
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NVVRS_PSEQ_INT_VENDOR2, /* Vendor Internal Fault Bit 2 */
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NVVRS_PSEQ_INT_VENDOR3, /* Vendor Internal Fault Bit 3 */
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NVVRS_PSEQ_INT_VENDOR4, /* Vendor Internal Fault Bit 4 */
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NVVRS_PSEQ_INT_VENDOR5, /* Vendor Internal Fault Bit 5 */
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NVVRS_PSEQ_INT_VENDOR6, /* Vendor Internal Fault Bit 6 */
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NVVRS_PSEQ_INT_VENDOR7, /* Vendor Internal Fault Bit 7 */
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};
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struct nvvrs_pseq_chip {
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struct device *dev;
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struct regmap *rmap;
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int chip_irq;
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struct i2c_client *client;
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struct regmap_irq_chip_data *irq_data;
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struct regmap_irq_chip *irq_chip;
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};
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#endif /* _MFD_NVIDIA_VRS_PSEQ_H_ */
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