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CONFIG_TEGRA_BWMGR is a downstream solution in the kernel before K5.15, and the implementation now is completed moved to BPMP side. Since it is not supported anymore, remove the legacy code for maintainability. Bug 4955427 Change-Id: I688c44288bfb8522ddfebd8abe294b0410ca8dc1 Signed-off-by: Johnny Liu <johnliu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3248363 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
257 lines
6.5 KiB
C
257 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2022, NVIDIA CORPORATION, All rights reserved.
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#ifndef __EMC_BWMGR_H
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#define __EMC_BWMGR_H
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/of_address.h>
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#include <linux/platform/tegra/iso_client.h>
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#include <soc/tegra/bpmp-abi.h>
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/* keep in sync with tegra_bwmgr_client_names */
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enum tegra_bwmgr_client_id {
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TEGRA_BWMGR_CLIENT_CPU_CLUSTER_0,
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TEGRA_BWMGR_CLIENT_CPU_CLUSTER_1,
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TEGRA_BWMGR_CLIENT_CPU_CLUSTER_2,
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TEGRA_BWMGR_CLIENT_CPU_CLUSTER_3,
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TEGRA_BWMGR_CLIENT_DISP0,
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TEGRA_BWMGR_CLIENT_DISP1,
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TEGRA_BWMGR_CLIENT_DISP2,
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TEGRA_BWMGR_CLIENT_DISP1_LA_EMC,
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TEGRA_BWMGR_CLIENT_DISP2_LA_EMC,
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TEGRA_BWMGR_CLIENT_USBD,
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TEGRA_BWMGR_CLIENT_XHCI,
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TEGRA_BWMGR_CLIENT_SDMMC1,
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TEGRA_BWMGR_CLIENT_SDMMC2,
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TEGRA_BWMGR_CLIENT_SDMMC3,
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TEGRA_BWMGR_CLIENT_SDMMC4,
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TEGRA_BWMGR_CLIENT_MON,
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TEGRA_BWMGR_CLIENT_GPU,
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TEGRA_BWMGR_CLIENT_MSENC,
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TEGRA_BWMGR_CLIENT_NVENC1,
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TEGRA_BWMGR_CLIENT_NVJPG,
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TEGRA_BWMGR_CLIENT_NVDEC,
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TEGRA_BWMGR_CLIENT_NVDEC1,
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TEGRA_BWMGR_CLIENT_TSEC,
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TEGRA_BWMGR_CLIENT_TSECB,
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TEGRA_BWMGR_CLIENT_VI,
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TEGRA_BWMGR_CLIENT_ISPA,
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TEGRA_BWMGR_CLIENT_ISPB,
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TEGRA_BWMGR_CLIENT_CAMERA,
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TEGRA_BWMGR_CLIENT_CAMERA_NON_ISO,
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TEGRA_BWMGR_CLIENT_CAMRTC,
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TEGRA_BWMGR_CLIENT_ISOMGR,
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TEGRA_BWMGR_CLIENT_THERMAL_CAP,
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TEGRA_BWMGR_CLIENT_VIC,
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TEGRA_BWMGR_CLIENT_APE_ADSP,
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TEGRA_BWMGR_CLIENT_APE_ADMA,
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TEGRA_BWMGR_CLIENT_PCIE,
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TEGRA_BWMGR_CLIENT_PCIE_1,
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TEGRA_BWMGR_CLIENT_PCIE_2,
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TEGRA_BWMGR_CLIENT_PCIE_3,
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TEGRA_BWMGR_CLIENT_PCIE_4,
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TEGRA_BWMGR_CLIENT_PCIE_5,
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TEGRA_BWMGR_CLIENT_BBC_0,
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TEGRA_BWMGR_CLIENT_EQOS,
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TEGRA_BWMGR_CLIENT_SE0,
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TEGRA_BWMGR_CLIENT_SE1,
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TEGRA_BWMGR_CLIENT_SE2,
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TEGRA_BWMGR_CLIENT_SE3,
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TEGRA_BWMGR_CLIENT_SE4,
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TEGRA_BWMGR_CLIENT_NVPMODEL,
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TEGRA_BWMGR_CLIENT_DEBUG,
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TEGRA_BWMGR_CLIENT_DLA0,
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TEGRA_BWMGR_CLIENT_DLA1,
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TEGRA_BWMGR_CLIENT_COUNT /* Should always be last */
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};
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enum tegra_bwmgr_request_type {
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TEGRA_BWMGR_SET_EMC_FLOOR, /* lower bound */
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TEGRA_BWMGR_SET_EMC_CAP, /* upper bound */
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TEGRA_BWMGR_SET_EMC_ISO_CAP, /* upper bound that affects ISO Bw */
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TEGRA_BWMGR_SET_EMC_SHARED_BW, /* shared bw request */
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TEGRA_BWMGR_SET_EMC_SHARED_BW_ISO, /* for use by ISO Mgr only */
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TEGRA_BWMGR_SET_EMC_REQ_COUNT /* Should always be last */
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};
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enum bwmgr_dram_types {
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DRAM_TYPE_NONE,
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DRAM_TYPE_LPDDR4_16CH_ECC,
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DRAM_TYPE_LPDDR4_8CH_ECC,
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DRAM_TYPE_LPDDR4_4CH_ECC,
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DRAM_TYPE_LPDDR4_2CH_ECC,
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DRAM_TYPE_LPDDR4_16CH,
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DRAM_TYPE_LPDDR4_8CH,
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DRAM_TYPE_LPDDR4_4CH,
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DRAM_TYPE_LPDDR4_2CH,
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DRAM_TYPE_LPDDR3_2CH,
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DRAM_TYPE_DDR3_2CH
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};
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extern u8 bwmgr_dram_efficiency;
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extern u8 bwmgr_dram_num_channels;
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/* flag to determine supported memory and channel configuration */
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extern u8 bwmgr_dram_config_supported;
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extern u32 *bwmgr_dram_iso_eff_table;
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extern u32 *bwmgr_dram_noniso_eff_table;
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extern u32 *bwmgr_max_nvdis_bw_reqd;
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extern u32 *bwmgr_max_vi_bw_reqd;
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extern int *bwmgr_slope;
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extern u32 *bwmgr_vi_bw_reqd_offset;
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extern int bwmgr_iso_bw_percentage;
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extern enum bwmgr_dram_types bwmgr_dram_type;
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extern int emc_to_dram_freq_factor;
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extern struct mrq_emc_dvfs_latency_response bwmgr_emc_dvfs;
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struct tegra_bwmgr_client;
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struct bwmgr_ops {
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unsigned long (*freq_to_bw)(unsigned long freq);
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unsigned long (*bw_to_freq)(unsigned long bw);
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u32 (*dvfs_latency)(u32 ufreq);
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unsigned long (*bwmgr_apply_efficiency)(
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unsigned long total_bw, unsigned long iso_bw,
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unsigned long max_rate, u64 usage_flags,
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unsigned long *iso_bw_min, unsigned long iso_bw_nvdis,
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unsigned long iso_bw_vi);
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unsigned long (*get_best_iso_freq)(long iso_bw,
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long iso_bw_nvdis, long iso_bw_vi);
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void (*update_efficiency)(unsigned long dram_refresh_rate);
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u32 (*get_max_iso_bw)(enum tegra_iso_client client);
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};
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struct bwmgr_ops *bwmgr_eff_init_t21x(void);
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struct bwmgr_ops *bwmgr_eff_init_t18x(void);
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struct bwmgr_ops *bwmgr_eff_init_t19x(void);
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static inline struct tegra_bwmgr_client *tegra_bwmgr_register(
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enum tegra_bwmgr_client_id client_id)
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{
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static int i;
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/* return a dummy handle to allow client to function
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* as if bwmgr were enabled.
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*/
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return (struct tegra_bwmgr_client *) &i;
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}
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static inline void tegra_bwmgr_unregister(struct tegra_bwmgr_client *handle) {}
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static inline int bwmgr_init(void)
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{
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return 0;
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}
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static inline void bwmgr_exit(void) {}
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static inline u8 tegra_bwmgr_get_dram_num_channels(void)
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{
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return 0;
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}
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static inline unsigned long tegra_bwmgr_get_emc_rate(void)
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{
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static struct clk *bwmgr_emc_clk;
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struct device_node *dn;
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if (!bwmgr_emc_clk) {
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dn = of_find_compatible_node(NULL, NULL, "nvidia,bwmgr");
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if (dn == NULL) {
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pr_err("bwmgr: dt node not found.\n");
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return 0;
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}
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bwmgr_emc_clk = of_clk_get(dn, 0);
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if (IS_ERR_OR_NULL(bwmgr_emc_clk)) {
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pr_err("bwmgr: couldn't find emc clock.\n");
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bwmgr_emc_clk = NULL;
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WARN_ON(true);
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return 0;
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}
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}
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return clk_get_rate(bwmgr_emc_clk);
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}
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static inline unsigned long tegra_bwmgr_get_max_emc_rate(void)
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{
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static struct clk *bwmgr_emc_clk;
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struct device_node *dn;
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if (!bwmgr_emc_clk) {
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dn = of_find_compatible_node(NULL, NULL, "nvidia,bwmgr");
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if (dn == NULL) {
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pr_err("bwmgr: dt node not found.\n");
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return 0;
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}
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bwmgr_emc_clk = of_clk_get(dn, 0);
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if (IS_ERR_OR_NULL(bwmgr_emc_clk)) {
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pr_err("bwmgr: couldn't find emc clock.\n");
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bwmgr_emc_clk = NULL;
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WARN_ON(true);
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return 0;
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}
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}
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/* Use LONG_MAX as clk_round_rate treats rate argument as signed */
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return clk_round_rate(bwmgr_emc_clk, LONG_MAX);
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}
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static inline unsigned long tegra_bwmgr_get_core_emc_rate(void)
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{
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return 0;
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}
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static inline unsigned long tegra_bwmgr_round_rate(unsigned long bw)
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{
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static struct clk *bwmgr_emc_clk;
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struct device_node *dn;
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if (!bwmgr_emc_clk) {
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dn = of_find_compatible_node(NULL, NULL, "nvidia,bwmgr");
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if (dn == NULL) {
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pr_err("bwmgr: dt node not found.\n");
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return 0;
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}
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bwmgr_emc_clk = of_clk_get(dn, 0);
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if (IS_ERR_OR_NULL(bwmgr_emc_clk)) {
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pr_err("bwmgr: couldn't find emc clock.\n");
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bwmgr_emc_clk = NULL;
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WARN_ON(true);
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return 0;
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}
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}
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return clk_round_rate(bwmgr_emc_clk, bw);
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}
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static inline int tegra_bwmgr_set_emc(struct tegra_bwmgr_client *handle,
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unsigned long val, enum tegra_bwmgr_request_type req)
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{
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return 0;
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}
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static inline int tegra_bwmgr_get_client_info(struct tegra_bwmgr_client *handle,
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unsigned long *out_val,
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enum tegra_bwmgr_request_type req)
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{
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if (!out_val)
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return -EINVAL;
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*out_val = 0;
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return 0;
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}
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static inline int tegra_bwmgr_notifier_register(struct notifier_block *nb)
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{
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return 0;
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}
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static inline int tegra_bwmgr_notifier_unregister(struct notifier_block *nb)
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{
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return 0;
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}
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#endif /* __EMC_BWMGR_H */
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