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856af79422
In order to avoid the VIC performance bottleneck from EMC, VIC needs to ask for the required memory bandwidth for itself according to its current frequency. Bug 4097374 Signed-off-by: Johnny Liu <johnliu@nvidia.com> Change-Id: Ieeeace34a935f96f949e5c8429f2f2b4edaa556c Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2897536 Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
38 lines
865 B
C
38 lines
865 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2023, NVIDIA Corporation. All rights reserved.
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*/
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#ifndef TEGRA_VIC_H
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#define TEGRA_VIC_H
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/* VIC methods */
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#define VIC_SET_FCE_UCODE_SIZE 0x0000071C
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#define VIC_SET_FCE_UCODE_OFFSET 0x0000072C
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/* VIC registers */
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#define NV_PVIC_MISC_PRI_VIC_CG 0x000016d0
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#define CG_IDLE_CG_DLY_CNT(val) ((val & 0x3f) << 0)
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#define CG_IDLE_CG_EN (1 << 6)
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#define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16)
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#define NV_PVIC_TFBIF_ACTMON_ACTIVE_WEIGHT 0x00002054
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#define VIC_TFBIF_TRANSCFG 0x00002044
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/* Firmware offsets */
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#define VIC_UCODE_FCE_HEADER_OFFSET (6*4)
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#define VIC_UCODE_FCE_DATA_OFFSET (7*4)
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#define FCE_UCODE_SIZE_OFFSET (2*4)
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/*
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* VIC AXI read bus is 256-bits width
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* VIC AXI write bus is 256-bits width
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*/
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#define VIC_AXI_RW_BANDWIDTH 512
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#endif /* TEGRA_VIC_H */
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