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86efe596c5
mc-utils driver support is needed on T264, and it should be present in nvidia-t264 repo, so as to avoid leaking any information. Also, we need to make sure once T264 is public the existing mc-utils driver can be updated easily for T264 support. Hence first copy the existing mc-utils driver from nvidia-oot into nvidia-t264, then make changes for T264 and finally when T264 is public, just cherry-pick the addional changes in nvidia-oot and clean up driver from nvidia-t264. This change is doing the first step i.e. copying existing mc-utils driver code from nvidia-oot into nvidia-t264. Bug 4090660 Change-Id: I95eff8d3f7fef267a5c0f0e2137c4343a615d4aa Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/2911970 Reviewed-by: Sachin Nikam <snikam@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
100 lines
2.7 KiB
C
100 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
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#ifndef __TEGRA_MC_UTILS_H
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#define __TEGRA_MC_UTILS_H
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enum dram_types {
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DRAM_TYPE_INVAL,
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DRAM_TYPE_LPDDR5_16CH_ECC_1RANK,
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DRAM_TYPE_LPDDR5_16CH_ECC_2RANK,
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DRAM_TYPE_LPDDR5_8CH_ECC_1RANK,
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DRAM_TYPE_LPDDR5_8CH_ECC_2RANK,
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DRAM_TYPE_LPDDR5_4CH_ECC_1RANK,
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DRAM_TYPE_LPDDR5_4CH_ECC_2RANK,
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DRAM_TYPE_LPDDR5_16CH_1RANK,
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DRAM_TYPE_LPDDR5_16CH_2RANK,
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DRAM_TYPE_LPDDR5_8CH_1RANK,
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DRAM_TYPE_LPDDR5_8CH_2RANK,
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DRAM_TYPE_LPDDR5_4CH_1RANK,
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DRAM_TYPE_LPDDR5_4CH_2RANK,
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DRAM_TYPE_LPDDR4_16CH_ECC_1RANK,
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DRAM_TYPE_LPDDR4_16CH_ECC_2RANK,
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DRAM_TYPE_LPDDR4_8CH_ECC_1RANK,
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DRAM_TYPE_LPDDR4_8CH_ECC_2RANK,
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DRAM_TYPE_LPDDR4_4CH_ECC_1RANK,
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DRAM_TYPE_LPDDR4_4CH_ECC_2RANK,
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DRAM_TYPE_LPDDR4_16CH_1RANK,
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DRAM_TYPE_LPDDR4_16CH_2RANK,
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DRAM_TYPE_LPDDR4_8CH_1RANK,
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DRAM_TYPE_LPDDR4_8CH_2RANK,
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DRAM_TYPE_LPDDR4_4CH_1RANK,
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DRAM_TYPE_LPDDR4_4CH_2RANK,
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};
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struct mc_utils_ops {
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unsigned long (*emc_freq_to_bw)(unsigned long freq);
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unsigned long (*emc_bw_to_freq)(unsigned long bw);
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enum dram_types (*tegra_dram_types)(void);
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u8 (*get_dram_num_channels)(void);
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unsigned long (*dram_clk_to_mc_clk)(unsigned long dram_clk);
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};
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/*
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* Utility API to convert the given frequency to Bandwidth.
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*
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* @freq Frequency to convert. It can be in any unit - the resulting Bandwidth
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* will be in the same unit as passed. E.g KHz leads to KBps and Hz
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* leads to Bps.
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*
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* Converts EMC clock frequency into theoretical BW. This
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* does not account for a realistic utilization of the EMC bus. That is the
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* various overheads (refresh, bank commands, etc) that a real system sees
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* are not computed.
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*
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* Return: Converted Bandwidth.
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*/
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unsigned long emc_freq_to_bw(unsigned long freq);
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/*
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* Utility API to convert the given Bandwidth to frequency.
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*
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* @bw Bandwidth to convert. It can be in any unit - the resulting frequency
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* will be in the same unit as passed. E.g KBps leads to KHz and Bps leads
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* to Hz.
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*
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* Converts BW into theoretical EMC clock frequency.
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*
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* Return: Converted Frequency.
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*/
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unsigned long emc_bw_to_freq(unsigned long bw);
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/*
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* Return dram types or dram configuration.
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*
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* Return dram configuration based upon ecc/channel/Rank
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*
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* Return: dram type.
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*/
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enum dram_types tegra_dram_types(void);
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/*
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* Return Number of channels of dram.
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*
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* Return number of dram channels
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*
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* Return: dram channels.
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*/
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u8 get_dram_num_channels(void);
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/*
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* Return mc_clk from dram_clk.
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*
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* Return DRAM clock in MHZ to MC clk in MHz.
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*
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* dram_clk: dram clk in MHz
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* Return: mc clk in MHz.
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*/
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unsigned long dram_clk_to_mc_clk(unsigned long dram_clk);
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#endif /* __TEGRA_MC_UTILS_H */
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