Rakesh Goyal 8708cf6e98 nvethernet: read ethernet hw counters periodically ...

HW MMC registers are 32 bits in size. Some of these will
overrun in few secs if there are live traffic at line rate.

Scheduling work queue to get periodic value from MMC
HW registers and update in 64 bits local variables, will
be solution to this HW limitation.

Bug 200544686

Change-Id: Ifc358f3f6b50839f7d9f48c2f98cb2cdd9ac0821
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2179298
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2022-11-01 14:27:07 +05:30

..

nvidia

nvethernet: read ethernet hw counters periodically

2022-11-01 14:27:07 +05:30

Makefile

net: ethernet: nvidia: add pcie vnet driver

2022-07-05 14:32:20 -07:00