mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 09:11:26 +03:00
8e36d59756
Resolve linux-5.8-rc3 merge conflicts in k5.9 branch (currently tracking mainline with linux-5.7.0) Fix build errors in k5.9 branch after merge of linux-5.8-rc3 bug 200617764 Change-Id: I3a358fef6e8b7c5926fd0de05a03cee539547e8f Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
373 lines
9.1 KiB
C
373 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* tegra_asoc_utils.c - Harmony machine ASoC driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (C) 2010,2012 - NVIDIA, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include "tegra_asoc_utils.h"
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/*
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* this will be used for platforms from Tegra210 onwards.
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* odd rates: sample rates multiple of 11.025kHz
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* even_rates: sample rates multiple of 8kHz
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*/
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enum rate_type {
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ODD_RATE,
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EVEN_RATE,
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NUM_RATE_TYPE,
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};
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unsigned int tegra210_pll_base_rate[NUM_RATE_TYPE] = {338688000, 368640000};
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unsigned int tegra186_pll_base_rate[NUM_RATE_TYPE] = {270950400, 245760000};
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unsigned int default_pll_out_rate[NUM_RATE_TYPE] = {45158400, 49152000};
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int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
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int mclk)
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{
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int new_baseclock;
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bool clk_change;
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int err;
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switch (srate) {
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case 11025:
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case 22050:
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case 44100:
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case 88200:
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if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
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new_baseclock = 56448000;
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else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
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new_baseclock = 564480000;
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else
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new_baseclock = 282240000;
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break;
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case 8000:
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case 16000:
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case 32000:
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case 48000:
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case 64000:
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case 96000:
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if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
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new_baseclock = 73728000;
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else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
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new_baseclock = 552960000;
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else
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new_baseclock = 368640000;
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break;
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default:
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return -EINVAL;
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}
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clk_change = ((new_baseclock != data->set_baseclock) ||
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(mclk != data->set_mclk));
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if (!clk_change)
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return 0;
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data->set_baseclock = 0;
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data->set_mclk = 0;
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clk_disable_unprepare(data->clk_cdev1);
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clk_disable_unprepare(data->clk_pll_a_out0);
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clk_disable_unprepare(data->clk_pll_a);
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err = clk_set_rate(data->clk_pll_a, new_baseclock);
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if (err) {
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dev_err(data->dev, "Can't set base pll rate: %d\n", err);
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return err;
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}
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err = clk_set_rate(data->clk_pll_a_out0, mclk);
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if (err) {
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dev_err(data->dev, "Can't set pll_out rate: %d\n", err);
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return err;
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}
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/* Don't set cdev1/extern1 rate; it's locked to pll_out */
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err = clk_prepare_enable(data->clk_pll_a);
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if (err) {
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dev_err(data->dev, "Can't enable pll: %d\n", err);
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return err;
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}
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err = clk_prepare_enable(data->clk_pll_a_out0);
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if (err) {
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dev_err(data->dev, "Can't enable pll_out: %d\n", err);
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return err;
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}
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err = clk_prepare_enable(data->clk_cdev1);
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if (err) {
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dev_err(data->dev, "Can't enable clk_cdev1: %d\n", err);
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return err;
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}
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data->set_baseclock = new_baseclock;
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data->set_mclk = mclk;
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_rate);
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int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data)
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{
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const int pll_rate = 73728000;
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const int ac97_rate = 24576000;
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int err;
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clk_disable_unprepare(data->clk_cdev1);
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clk_disable_unprepare(data->clk_pll_a_out0);
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clk_disable_unprepare(data->clk_pll_a);
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/*
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* AC97 rate is fixed at 24.576MHz and is used for both the host
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* controller and the external codec
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*/
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err = clk_set_rate(data->clk_pll_a, pll_rate);
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if (err) {
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dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
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return err;
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}
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err = clk_set_rate(data->clk_pll_a_out0, ac97_rate);
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if (err) {
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dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
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return err;
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}
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/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
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err = clk_prepare_enable(data->clk_pll_a);
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if (err) {
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dev_err(data->dev, "Can't enable pll_a: %d\n", err);
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return err;
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}
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err = clk_prepare_enable(data->clk_pll_a_out0);
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if (err) {
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dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
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return err;
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}
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err = clk_prepare_enable(data->clk_cdev1);
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if (err) {
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dev_err(data->dev, "Can't enable cdev1: %d\n", err);
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return err;
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}
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data->set_baseclock = pll_rate;
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data->set_mclk = ac97_rate;
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_ac97_rate);
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int tegra_asoc_utils_set_tegra210_rate(struct tegra_asoc_utils_data *data,
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unsigned int sample_rate)
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{
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unsigned int new_pll_base, pll_out, aud_mclk = 0;
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int err;
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switch (sample_rate) {
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case 11025:
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case 22050:
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case 44100:
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case 88200:
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case 176400:
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new_pll_base = data->pll_base_rate[ODD_RATE];
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pll_out = default_pll_out_rate[ODD_RATE];
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break;
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case 8000:
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case 16000:
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case 32000:
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case 48000:
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case 96000:
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case 192000:
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new_pll_base = data->pll_base_rate[EVEN_RATE];
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pll_out = default_pll_out_rate[EVEN_RATE];
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break;
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default:
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return -EINVAL;
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}
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/* reduce pll_out rate to support lower sampling rates */
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if (sample_rate <= 11025)
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pll_out = pll_out >> 1;
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if (data->mclk_fs)
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aud_mclk = sample_rate * data->mclk_fs;
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if (data->set_baseclock != new_pll_base) {
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err = clk_set_rate(data->clk_pll_a, new_pll_base);
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if (err) {
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dev_err(data->dev, "Can't set clk_pll_a rate: %d\n",
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err);
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return err;
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}
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data->set_baseclock = new_pll_base;
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}
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if (data->set_pll_out != pll_out) {
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err = clk_set_rate(data->clk_pll_a_out0, pll_out);
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if (err) {
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dev_err(data->dev, "Can't set clk_pll_a_out0 rate: %d\n",
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err);
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return err;
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}
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data->set_pll_out = pll_out;
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}
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if (data->set_mclk != aud_mclk) {
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err = clk_set_rate(data->clk_cdev1, aud_mclk);
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if (err) {
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dev_err(data->dev, "Can't set clk_cdev1 rate: %d\n",
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err);
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return err;
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}
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data->set_mclk = aud_mclk;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_tegra210_rate);
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int tegra_asoc_utils_clk_enable(struct tegra_asoc_utils_data *data)
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{
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int err;
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err = clk_prepare_enable(data->clk_cdev1);
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if (err) {
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dev_err(data->dev, "Can't enable clock cdev1\n");
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return err;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_clk_enable);
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void tegra_asoc_utils_clk_disable(struct tegra_asoc_utils_data *data)
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{
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clk_disable_unprepare(data->clk_cdev1);
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_clk_disable);
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int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
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struct device *dev)
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{
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struct clk *clk_out_1, *clk_extern1;
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int ret;
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data->dev = dev;
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if (of_machine_is_compatible("nvidia,tegra20"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20;
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else if (of_machine_is_compatible("nvidia,tegra30"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA30;
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else if (of_machine_is_compatible("nvidia,tegra114"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA114;
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else if (of_machine_is_compatible("nvidia,tegra124"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA124;
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else if (of_machine_is_compatible("nvidia,tegra210"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA210;
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else if (of_machine_is_compatible("nvidia,tegra186"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA186;
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else if (of_machine_is_compatible("nvidia,tegra194"))
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data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA194;
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else {
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dev_err(data->dev, "SoC unknown to Tegra ASoC utils\n");
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return -EINVAL;
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}
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data->clk_pll_a = devm_clk_get(dev, "pll_a");
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if (IS_ERR(data->clk_pll_a)) {
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dev_err(data->dev, "Can't retrieve clk pll_a\n");
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return PTR_ERR(data->clk_pll_a);
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}
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data->clk_pll_a_out0 = devm_clk_get(dev, "pll_a_out0");
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if (IS_ERR(data->clk_pll_a_out0)) {
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dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
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return PTR_ERR(data->clk_pll_a_out0);
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}
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/* FIXME: data->clk_cdev1 = devm_clk_get(dev, "mclk"); */
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data->clk_cdev1 = devm_clk_get(dev, "extern1");
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if (IS_ERR(data->clk_cdev1)) {
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dev_err(data->dev, "Can't retrieve clk cdev1\n");
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return PTR_ERR(data->clk_cdev1);
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}
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if (data->soc < TEGRA_ASOC_UTILS_SOC_TEGRA210) {
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ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
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if (ret)
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return ret;
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}
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if (data->soc < TEGRA_ASOC_UTILS_SOC_TEGRA186)
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data->pll_base_rate = tegra210_pll_base_rate;
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else
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data->pll_base_rate = tegra186_pll_base_rate;
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/*
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* If clock parents are not set in DT, configure here to use clk_out_1
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* as mclk and extern1 as parent for Tegra30 and higher.
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*/
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if (!of_find_property(dev->of_node, "assigned-clock-parents", NULL) &&
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data->soc > TEGRA_ASOC_UTILS_SOC_TEGRA20) {
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dev_warn(data->dev,
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"Configuring clocks for a legacy device-tree\n");
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dev_warn(data->dev,
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"Please update DT to use assigned-clock-parents\n");
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clk_extern1 = devm_clk_get(dev, "extern1");
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if (IS_ERR(clk_extern1)) {
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dev_err(data->dev, "Can't retrieve clk extern1\n");
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return PTR_ERR(clk_extern1);
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}
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ret = clk_set_parent(clk_extern1, data->clk_pll_a_out0);
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if (ret < 0) {
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dev_err(data->dev,
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"Set parent failed for clk extern1\n");
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return ret;
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}
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clk_out_1 = devm_clk_get(dev, "pmc_clk_out_1");
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if (IS_ERR(clk_out_1)) {
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dev_err(data->dev, "Can't retrieve pmc_clk_out_1\n");
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return PTR_ERR(clk_out_1);
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}
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ret = clk_set_parent(clk_out_1, clk_extern1);
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if (ret < 0) {
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dev_err(data->dev,
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"Set parent failed for pmc_clk_out_1\n");
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return ret;
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}
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data->clk_cdev1 = clk_out_1;
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}
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/*
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* FIXME: There is some unknown dependency between audio mclk disable
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* and suspend-resume functionality on Tegra30, although audio mclk is
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* only needed for audio.
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*/
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ret = clk_prepare_enable(data->clk_cdev1);
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if (ret) {
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dev_err(data->dev, "Can't enable cdev1: %d\n", ret);
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
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MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
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MODULE_DESCRIPTION("Tegra ASoC utility code");
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MODULE_LICENSE("GPL");
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