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8f1271978c
- Start using OS abstraction for all utility functions. JIRA TDS-16052 Change-Id: Ic1e0f059194e15ff7dff0fa97997bd0d69dfc58c Signed-off-by: anupamg <anupamg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3172545 Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Arun Swain <arswain@nvidia.com>
74 lines
1.4 KiB
C
74 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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#include <dce.h>
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#include <dce-log.h>
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#include <os-utils.h>
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enum pm_controls {
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FW_LOAD_HALTED,
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FW_LOAD_DONE
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};
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/**
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* dce_evp_set_reset_addr - Writes to the evp reset addr register.
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*
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* @d : Pointer to struct tegra_dce
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* @addr : 32bit address
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*
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* Return : Void
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*/
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static inline void dce_evp_set_reset_addr(struct tegra_dce *d, u32 addr)
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{
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dce_writel(d, evp_reset_addr_r(), addr);
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}
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/**
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* dce_pm_set_pm_ctrl - Writes to the reset control register.
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*
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* @d : Pointer to struct tegra_dce
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* @val : Value to programmed to the register
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*
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* Return : Void
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*/
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static void dce_pm_set_pm_ctrl(struct tegra_dce *d, enum pm_controls val)
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{
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switch (val) {
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case FW_LOAD_DONE:
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dce_writel(d, pm_r5_ctrl_r(), pm_r5_ctrl_fwloaddone_done_f());
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break;
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case FW_LOAD_HALTED:
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dce_writel(d, pm_r5_ctrl_r(), pm_r5_ctrl_fwloaddone_halted_f());
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break;
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default:
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break;
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}
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}
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/**
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* dce_reset_dce - Configures the pertinent registers in
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* DCE cluser to reset DCE.
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*
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* @d : Pointer to tegra_dce struct.
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*
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* Return : 0 if success
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*/
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int dce_reset_dce(struct tegra_dce *d)
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{
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u32 fw_dce_addr;
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if (!d->fw_data) {
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dce_err(d, "No fw_data present");
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return -1;
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}
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fw_dce_addr = dce_get_fw_dce_addr(d);
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dce_evp_set_reset_addr(d, fw_dce_addr);
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dce_pm_set_pm_ctrl(d, FW_LOAD_DONE);
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return 0;
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}
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