mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-25 10:42:21 +03:00
8f8c3d0aa9
Set default register values for AHUB modules in regmap. This will ensure after runtime suspend/resume AHUB register POR values does not get reset to 0. Bug 200039212 Change-Id: I38e4c04721450b7511404c0db2911b314b68a880 Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-on: http://git-master/r/603339
483 lines
13 KiB
C
483 lines
13 KiB
C
/*
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* tegra210_dmic_alt.c - Tegra210 DMIC driver
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*
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* Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/of_device.h>
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#include <linux/debugfs.h>
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#include "tegra210_xbar_alt.h"
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#include "tegra210_dmic_alt.h"
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#include "ahub_unit_fpga_clock.h"
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#define DRV_NAME "tegra210-dmic"
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static const struct reg_default tegra210_dmic_reg_defaults[] = {
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{ TEGRA210_DMIC_TX_INT_MASK, 0x00000001},
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{ TEGRA210_DMIC_TX_CIF_CTRL, 0x00007700},
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{ TEGRA210_DMIC_CG, 0x1},
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{ TEGRA210_DMIC_CTRL, 0x00000301},
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{ TEGRA210_DMIC_DCR_FILTER_GAIN, 0x00800000},
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{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_0, 0x00800000},
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{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_1, 0xff800000},
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{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_3, 0xff800347},
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{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4, 0xffc0ff97},
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{ TEGRA210_DMIC_LP_FILTER_GAIN, 0x004c255a},
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{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_0, 0x00800000},
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{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_1, 0x00ffa74b},
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{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_2, 0x00800000},
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{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_3, 0x009e382a},
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{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_4, 0x00380f38},
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{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_0, 0x00800000},
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{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_1, 0x00fe1178},
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{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_2, 0x00800000},
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{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_3, 0x00e05f02},
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{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_4, 0x006fc80d},
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{ TEGRA210_DMIC_CORRECTION_FILTER_GAIN, 0x010628f6},
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{ TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_0, 0x00800000},
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{ TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_3, 0x0067ffff},
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{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_0, 0x00800000},
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{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_1, 0x0048f5c2},
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{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_3, 0x00562394},
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{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_4, 0x00169446},
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};
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static int tegra210_dmic_runtime_suspend(struct device *dev)
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{
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struct tegra210_dmic *dmic = dev_get_drvdata(dev);
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regcache_cache_only(dmic->regmap, true);
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#ifndef CONFIG_MACH_GRENADA
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clk_disable_unprepare(dmic->clk_dmic);
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#endif
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pm_runtime_put_sync(dev->parent);
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return 0;
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}
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static int tegra210_dmic_runtime_resume(struct device *dev)
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{
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struct tegra210_dmic *dmic = dev_get_drvdata(dev);
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int ret;
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ret = pm_runtime_get_sync(dev->parent);
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if (ret < 0) {
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dev_err(dev, "parent get_sync failed: %d\n", ret);
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return ret;
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}
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#ifndef CONFIG_MACH_GRENADA
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ret = clk_prepare_enable(dmic->clk_dmic);
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if (ret) {
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dev_err(dev, "clk_enable failed: %d\n", ret);
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return ret;
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}
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#endif
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regcache_cache_only(dmic->regmap, false);
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regcache_sync(dmic->regmap);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra210_dmic_suspend(struct device *dev)
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{
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struct tegra210_dmic *dmic = dev_get_drvdata(dev);
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regcache_mark_dirty(dmic->regmap);
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return 0;
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}
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#endif
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static int tegra210_dmic_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->dev;
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struct tegra210_dmic *dmic = snd_soc_dai_get_drvdata(dai);
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int channels, srate, dmic_clk, osr = TEGRA210_DMIC_OSR_64;
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struct tegra210_xbar_cif_conf cif_conf;
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channels = params_channels(params);
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srate = params_rate(params);
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dmic_clk = (1 << (6+osr)) * (srate/2);
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#ifdef CONFIG_MACH_GRENADA
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program_dmic_gpio();
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program_dmic_clk(dmic_clk);
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#endif
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regmap_update_bits(dmic->regmap,
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TEGRA210_DMIC_CTRL,
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TEGRA210_DMIC_CTRL_OSR_MASK,
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osr << TEGRA210_DMIC_CTRL_OSR_SHIFT);
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regmap_update_bits(dmic->regmap,
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TEGRA210_DMIC_DBG_CTRL,
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TEGRA210_DMIC_DBG_CTRL_SC_ENABLE,
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TEGRA210_DMIC_DBG_CTRL_SC_ENABLE);
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regmap_update_bits(dmic->regmap,
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TEGRA210_DMIC_CTRL,
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TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK,
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((1 << channels) - 1) <<
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TEGRA210_DMIC_CTRL_CHANNEL_SELECT_SHIFT);
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cif_conf.threshold = 0;
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cif_conf.audio_channels = channels;
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cif_conf.client_channels = channels;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_32;
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break;
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default:
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dev_err(dev, "Wrong format!\n");
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return -EINVAL;
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}
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cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_24;
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cif_conf.expand = 0;
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cif_conf.stereo_conv = 0;
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cif_conf.replicate = 0;
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cif_conf.truncate = 0;
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cif_conf.mono_conv = 0;
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dmic->soc_data->set_audio_cif(dmic->regmap, TEGRA210_DMIC_TX_CIF_CTRL,
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&cif_conf);
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return 0;
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}
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static int tegra210_dmic_codec_probe(struct snd_soc_codec *codec)
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{
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struct tegra210_dmic *dmic = snd_soc_codec_get_drvdata(codec);
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int ret;
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codec->control_data = dmic->regmap;
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ret = snd_soc_codec_set_cache_io(codec, 32, 32, SND_SOC_REGMAP);
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if (ret != 0) {
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dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static struct snd_soc_dai_ops tegra210_dmic_dai_ops = {
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.hw_params = tegra210_dmic_hw_params,
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};
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static struct snd_soc_dai_driver tegra210_dmic_dais[] = {
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{
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.name = "CIF",
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.capture = {
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.stream_name = "DMIC Transmit",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.ops = &tegra210_dmic_dai_ops,
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.symmetric_rates = 1,
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},
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{
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.name = "DAP",
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.playback = {
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.stream_name = "DMIC Receive",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.ops = &tegra210_dmic_dai_ops,
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.symmetric_rates = 1,
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}
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};
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static const struct snd_soc_dapm_widget tegra210_dmic_widgets[] = {
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SND_SOC_DAPM_AIF_OUT("DMIC TX", NULL, 0, SND_SOC_NOPM,
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0, 0),
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SND_SOC_DAPM_AIF_IN("DMIC RX", NULL, 0, TEGRA210_DMIC_ENABLE,
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TEGRA210_DMIC_ENABLE_EN_SHIFT, 0),
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};
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static const struct snd_soc_dapm_route tegra210_dmic_routes[] = {
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{ "DMIC RX", NULL, "DMIC Receive" },
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{ "DMIC TX", NULL, "DMIC RX" },
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{ "DMIC Transmit", NULL, "DMIC TX" },
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};
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static struct snd_soc_codec_driver tegra210_dmic_codec = {
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.probe = tegra210_dmic_codec_probe,
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.dapm_widgets = tegra210_dmic_widgets,
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.num_dapm_widgets = ARRAY_SIZE(tegra210_dmic_widgets),
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.dapm_routes = tegra210_dmic_routes,
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.num_dapm_routes = ARRAY_SIZE(tegra210_dmic_routes),
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.idle_bias_off = 1,
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};
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/* Regmap callback functions */
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static bool tegra210_dmic_wr_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_DMIC_TX_INT_MASK:
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case TEGRA210_DMIC_TX_INT_SET:
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case TEGRA210_DMIC_TX_INT_CLEAR:
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case TEGRA210_DMIC_TX_CIF_CTRL:
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case TEGRA210_DMIC_ENABLE:
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case TEGRA210_DMIC_SOFT_RESET:
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case TEGRA210_DMIC_CG:
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case TEGRA210_DMIC_CTRL:
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return true;
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default:
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if (((reg % 4) == 0) && (reg >= TEGRA210_DMIC_DBG_CTRL) &&
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(reg <= TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_4))
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return true;
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else
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return false;
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};
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}
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static bool tegra210_dmic_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_DMIC_TX_STATUS:
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case TEGRA210_DMIC_TX_INT_STATUS:
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case TEGRA210_DMIC_TX_INT_MASK:
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case TEGRA210_DMIC_TX_INT_SET:
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case TEGRA210_DMIC_TX_INT_CLEAR:
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case TEGRA210_DMIC_TX_CIF_CTRL:
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case TEGRA210_DMIC_ENABLE:
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case TEGRA210_DMIC_SOFT_RESET:
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case TEGRA210_DMIC_CG:
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case TEGRA210_DMIC_STATUS:
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case TEGRA210_DMIC_INT_STATUS:
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case TEGRA210_DMIC_CTRL:
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return true;
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default:
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if (((reg % 4) == 0) && (reg >= TEGRA210_DMIC_DBG_CTRL) &&
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(reg <= TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_4))
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return true;
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else
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return false;
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};
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}
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static bool tegra210_dmic_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_DMIC_TX_STATUS:
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case TEGRA210_DMIC_TX_INT_STATUS:
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case TEGRA210_DMIC_TX_INT_SET:
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case TEGRA210_DMIC_SOFT_RESET:
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case TEGRA210_DMIC_STATUS:
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case TEGRA210_DMIC_INT_STATUS:
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return true;
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default:
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return false;
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};
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}
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static const struct regmap_config tegra210_dmic_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_4,
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.writeable_reg = tegra210_dmic_wr_reg,
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.readable_reg = tegra210_dmic_rd_reg,
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.volatile_reg = tegra210_dmic_volatile_reg,
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.precious_reg = NULL,
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.reg_defaults = tegra210_dmic_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(tegra210_dmic_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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static const struct tegra210_dmic_soc_data soc_data_tegra210 = {
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.set_audio_cif = tegra210_xbar_set_cif,
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};
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static const struct of_device_id tegra210_dmic_of_match[] = {
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{ .compatible = "nvidia,tegra210-dmic", .data = &soc_data_tegra210 },
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{},
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};
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static int tegra210_dmic_platform_probe(struct platform_device *pdev)
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{
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struct tegra210_dmic *dmic;
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struct resource *mem, *memregion;
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void __iomem *regs;
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int ret = 0;
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const struct of_device_id *match;
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struct tegra210_dmic_soc_data *soc_data;
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match = of_match_device(tegra210_dmic_of_match, &pdev->dev);
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if (!match) {
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dev_err(&pdev->dev, "Error: No device match found\n");
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ret = -ENODEV;
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goto err;
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}
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soc_data = (struct tegra210_dmic_soc_data *)match->data;
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dmic = devm_kzalloc(&pdev->dev, sizeof(struct tegra210_dmic), GFP_KERNEL);
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if (!dmic) {
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dev_err(&pdev->dev, "Can't allocate dmic\n");
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ret = -ENOMEM;
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goto err;
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}
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dev_set_drvdata(&pdev->dev, dmic);
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dmic->soc_data = soc_data;
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#ifndef CONFIG_MACH_GRENADA
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dmic->clk_dmic = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(dmic->clk_dmic)) {
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dev_err(&pdev->dev, "Can't retrieve dmic clock\n");
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ret = PTR_ERR(dmic->clk_dmic);
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goto err;
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}
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#endif
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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dev_err(&pdev->dev, "No memory resource\n");
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ret = -ENODEV;
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goto err_clk_put;
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}
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memregion = devm_request_mem_region(&pdev->dev, mem->start,
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resource_size(mem), pdev->name);
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if (!memregion) {
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dev_err(&pdev->dev, "Memory region already claimed\n");
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ret = -EBUSY;
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goto err_clk_put;
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}
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regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
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if (!regs) {
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dev_err(&pdev->dev, "ioremap failed\n");
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ret = -ENOMEM;
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goto err_clk_put;
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}
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dmic->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
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&tegra210_dmic_regmap_config);
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if (IS_ERR(dmic->regmap)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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ret = PTR_ERR(dmic->regmap);
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goto err_clk_put;
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}
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regcache_cache_only(dmic->regmap, true);
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if (of_property_read_u32(pdev->dev.of_node,
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"nvidia,ahub-dmic-id",
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&pdev->dev.id) < 0) {
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dev_err(&pdev->dev,
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"Missing property nvidia,ahub-dmic-id\n");
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ret = -ENODEV;
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goto err_clk_put;
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}
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pm_runtime_enable(&pdev->dev);
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if (!pm_runtime_enabled(&pdev->dev)) {
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ret = tegra210_dmic_runtime_resume(&pdev->dev);
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if (ret)
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goto err_pm_disable;
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}
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ret = snd_soc_register_codec(&pdev->dev, &tegra210_dmic_codec,
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tegra210_dmic_dais,
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ARRAY_SIZE(tegra210_dmic_dais));
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if (ret != 0) {
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dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
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goto err_suspend;
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}
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return 0;
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err_suspend:
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if (!pm_runtime_status_suspended(&pdev->dev))
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tegra210_dmic_runtime_suspend(&pdev->dev);
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err_pm_disable:
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pm_runtime_disable(&pdev->dev);
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err_clk_put:
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#ifndef CONFIG_MACH_GRENADA
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devm_clk_put(&pdev->dev, dmic->clk_dmic);
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#endif
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err:
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return ret;
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}
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static int tegra210_dmic_platform_remove(struct platform_device *pdev)
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{
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struct tegra210_dmic *dmic;
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|
|
|
dmic = dev_get_drvdata(&pdev->dev);
|
|
snd_soc_unregister_codec(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra210_dmic_runtime_suspend(&pdev->dev);
|
|
|
|
#ifndef CONFIG_MACH_GRENADA
|
|
devm_clk_put(&pdev->dev, dmic->clk_dmic);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra210_dmic_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra210_dmic_runtime_suspend,
|
|
tegra210_dmic_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra210_dmic_suspend, NULL)
|
|
};
|
|
|
|
static struct platform_driver tegra210_dmic_driver = {
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = tegra210_dmic_of_match,
|
|
.pm = &tegra210_dmic_pm_ops,
|
|
},
|
|
.probe = tegra210_dmic_platform_probe,
|
|
.remove = tegra210_dmic_platform_remove,
|
|
};
|
|
module_platform_driver(tegra210_dmic_driver)
|
|
|
|
MODULE_AUTHOR("Rahul Mittal <rmittal@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra210 DMIC ASoC driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
MODULE_DEVICE_TABLE(of, tegra210_dmic_of_match);
|