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92ac7bc35a
Port camera drivers below from /kenrel/nvidia to /kernel/nvidia-oot as OOT modules: - Fusa-capture driver - Tegra V4L2 framework driver - vi/csi driver - tegra camera platform driver Change-Id: I390af27096425bb11e0934201dd1a90f001bb3fa Signed-off-by: Frank Chen <frankc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2780698 Reviewed-by: FNU Raunak <fraunak@nvidia.com> Reviewed-by: Ankur Pawar <ankurp@nvidia.com> Reviewed-by: Shiva Dubey <sdubey@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
43 lines
1.1 KiB
C
43 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Tegra 19x CSI register offsets
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*
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* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __CSI5_REGISTERS_H__
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#define __CSI5_REGISTERS_H__
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#define CSI5_BASE_ADDRESS 0x011000
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#define CSI5_PHY_OFFSET 0x010000
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#define CSI5_TEGRA_CSI_STREAM_0_BASE 0x10000
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#define CSI5_TEGRA_CSI_STREAM_2_BASE 0x20000
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#define CSI5_TEGRA_CSI_STREAM_4_BASE 0x30000
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#define CSI5_NVCSI_CIL_A_SW_RESET 0x24
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#define CSI5_NVCSI_CIL_B_SW_RESET 0xb0
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#define CSI5_SW_RESET1_EN (0x1 << 1)
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#define CSI5_SW_RESET0_EN (0x1 << 0)
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#define CSI5_E_INPUT_LP_IO1_SHIFT 22
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#define CSI5_E_INPUT_LP_IO0_SHIFT 21
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#define CSI5_E_INPUT_LP_CLK_SHIFT 20
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#define CSI5_E_INPUT_LP_IO1 (0x1 << 22)
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#define CSI5_E_INPUT_LP_IO0 (0x1 << 21)
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#define CSI5_E_INPUT_LP_CLK (0x1 << 20)
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#define CSI5_PD_CLK (0x1 << 18)
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#define CSI5_PD_IO1 (0x1 << 17)
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#define CSI5_PD_IO0 (0x1 << 16)
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#define CSI5_PD_CLK_SHIFT 18
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#define CSI5_PD_IO1_SHIFT 17
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#define CSI5_PD_IO0_SHIFT 16
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/* MIPICAL */
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#define CSI5_NVCSI_CIL_A_BASE 0x24
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#define CSI5_NVCSI_CIL_B_BASE 0xb0
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#define CSI5_PAD_CONFIG_0 0x8
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#endif /* __CSI5_REGISTERS_H__ */
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