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git://nv-tegra.nvidia.com/linux-nv-oot.git
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92ac7bc35a
Port camera drivers below from /kenrel/nvidia to /kernel/nvidia-oot as OOT modules: - Fusa-capture driver - Tegra V4L2 framework driver - vi/csi driver - tegra camera platform driver Change-Id: I390af27096425bb11e0934201dd1a90f001bb3fa Signed-off-by: Frank Chen <frankc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2780698 Reviewed-by: FNU Raunak <fraunak@nvidia.com> Reviewed-by: Ankur Pawar <ankurp@nvidia.com> Reviewed-by: Shiva Dubey <sdubey@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
217 lines
8.0 KiB
C
217 lines
8.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Tegra VI/CSI register offsets
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*
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* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __REGISTERS_H__
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#define __REGISTERS_H__
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/* VI registers */
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#define TEGRA_VI_SYNCPT_WAIT_TIMEOUT 200
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#define TEGRA_VI_CFG_VI_INCR_SYNCPT 0x000
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#define VI_CFG_VI_INCR_SYNCPT_COND(x) (x << 8)
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#define VI_CSI_PP_LINE_START(port) (4 + (port) * 4)
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#define VI_CSI_PP_FRAME_START(port) (5 + (port) * 4)
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#define VI_CSI_MW_REQ_DONE(port) (6 + (port) * 4)
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#define VI_CSI_MW_ACK_DONE(port) (7 + (port) * 4)
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#define TEGRA_VI_CFG_VI_INCR_SYNCPT_CNTRL 0x004
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#define TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR 0x008
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#define TEGRA_VI_CFG_CTXSW 0x020
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#define TEGRA_VI_CFG_INTSTATUS 0x024
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#define TEGRA_VI_CFG_PWM_CONTROL 0x038
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#define TEGRA_VI_CFG_PWM_HIGH_PULSE 0x03c
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#define TEGRA_VI_CFG_PWM_LOW_PULSE 0x040
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#define TEGRA_VI_CFG_PWM_SELECT_PULSE_A 0x044
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#define TEGRA_VI_CFG_PWM_SELECT_PULSE_B 0x048
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#define TEGRA_VI_CFG_PWM_SELECT_PULSE_C 0x04c
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#define TEGRA_VI_CFG_PWM_SELECT_PULSE_D 0x050
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#define TEGRA_VI_CFG_VGP1 0x064
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#define TEGRA_VI_CFG_VGP2 0x068
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#define TEGRA_VI_CFG_VGP3 0x06c
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#define TEGRA_VI_CFG_VGP4 0x070
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#define TEGRA_VI_CFG_VGP5 0x074
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#define TEGRA_VI_CFG_VGP6 0x078
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#define TEGRA_VI_CFG_INTERRUPT_MASK 0x08c
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#define TEGRA_VI_CFG_INTERRUPT_TYPE_SELECT 0x090
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#define TEGRA_VI_CFG_INTERRUPT_POLARITY_SELECT 0x094
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#define TEGRA_VI_CFG_INTERRUPT_STATUS 0x098
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#define TEGRA_VI_CFG_VGP_SYNCPT_CONFIG 0x0ac
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#define TEGRA_VI_CFG_VI_SW_RESET 0x0b4
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#define TEGRA_VI_CFG_CG_CTRL 0x0b8
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#define VI_CG_2ND_LEVEL_EN 0x1
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#define TEGRA_VI_CFG_VI_MCCIF_FIFOCTRL 0x0e4
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#define TEGRA_VI_CFG_TIMEOUT_WCOAL_VI 0x0e8
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#define TEGRA_VI_CFG_DVFS 0x0f0
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#define TEGRA_VI_CFG_RESERVE 0x0f4
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#define TEGRA_VI_CFG_RESERVE_1 0x0f8
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/* CSI registers */
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#define TEGRA_VI_CSI_BASE(x) (0x100 + (x) * 0x100)
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#define TEGRA_VI_CSI_SW_RESET 0x000
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#define TEGRA_VI_CSI_SINGLE_SHOT 0x004
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#define SINGLE_SHOT_CAPTURE 0x1
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#define CAPTURE_GOOD_FRAME 0x1
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#define TEGRA_VI_CSI_SINGLE_SHOT_STATE_UPDATE 0x008
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#define TEGRA_VI_CSI_IMAGE_DEF 0x00c
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#define BYPASS_PXL_TRANSFORM_OFFSET 24
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#define IMAGE_DEF_FORMAT_OFFSET 16
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#define IMAGE_DEF_DEST_MEM 0x1
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#define TEGRA_VI_CSI_RGB2Y_CTRL 0x010
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#define TEGRA_VI_CSI_MEM_TILING 0x014
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#define TEGRA_VI_CSI_IMAGE_SIZE 0x018
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#define IMAGE_SIZE_HEIGHT_OFFSET 16
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#define TEGRA_VI_CSI_IMAGE_SIZE_WC 0x01c
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#define TEGRA_VI_CSI_IMAGE_DT 0x020
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#define TEGRA_VI_CSI_SURFACE0_OFFSET_MSB 0x024
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#define TEGRA_VI_CSI_SURFACE0_OFFSET_LSB 0x028
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#define TEGRA_VI_CSI_SURFACE1_OFFSET_MSB 0x02c
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#define TEGRA_VI_CSI_SURFACE1_OFFSET_LSB 0x030
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#define TEGRA_VI_CSI_SURFACE2_OFFSET_MSB 0x034
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#define TEGRA_VI_CSI_SURFACE2_OFFSET_LSB 0x038
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#define TEGRA_VI_CSI_SURFACE0_BF_OFFSET_MSB 0x03c
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#define TEGRA_VI_CSI_SURFACE0_BF_OFFSET_LSB 0x040
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#define TEGRA_VI_CSI_SURFACE1_BF_OFFSET_MSB 0x044
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#define TEGRA_VI_CSI_SURFACE1_BF_OFFSET_LSB 0x048
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#define TEGRA_VI_CSI_SURFACE2_BF_OFFSET_MSB 0x04c
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#define TEGRA_VI_CSI_SURFACE2_BF_OFFSET_LSB 0x050
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#define TEGRA_VI_CSI_SURFACE0_STRIDE 0x054
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#define TEGRA_VI_CSI_SURFACE1_STRIDE 0x058
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#define TEGRA_VI_CSI_SURFACE2_STRIDE 0x05c
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#define TEGRA_VI_CSI_SURFACE_HEIGHT0 0x060
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#define TEGRA_VI_CSI_ISPINTF_CONFIG 0x064
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#define TEGRA_VI_CSI_ERROR_STATUS 0x084
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#define TEGRA_VI_CSI_ERROR_INT_MASK 0x088
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#define TEGRA_VI_CSI_WD_CTRL 0x08c
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#define TEGRA_VI_CSI_WD_PERIOD 0x090
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/* CSI Pixel Parser registers: Starts from 0x838, offset 0x0 */
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#define TEGRA_CSI_INPUT_STREAM_CONTROL 0x000
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#define CSI_SKIP_PACKET_THRESHOLD_OFFSET 16
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#define TEGRA_CSI_PIXEL_STREAM_CONTROL0 0x004
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#define CSI_PP_PACKET_HEADER_SENT (0x1 << 4)
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#define CSI_PP_DATA_IDENTIFIER_ENABLE (0x1 << 5)
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#define CSI_PP_WORD_COUNT_SELECT_HEADER (0x1 << 6)
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#define CSI_PP_CRC_CHECK_ENABLE (0x1 << 7)
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#define CSI_PP_WC_CHECK (0x1 << 8)
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#define CSI_PP_OUTPUT_FORMAT_STORE (0x3 << 16)
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#define CSI_PPA_PAD_LINE_NOPAD (0x2 << 24)
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#define CSI_PP_HEADER_EC_DISABLE (0x1 << 27)
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#define CSI_PPA_PAD_FRAME_NOPAD (0x2 << 28)
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#define TEGRA_CSI_PIXEL_STREAM_CONTROL1 0x008
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#define CSI_PP_TOP_FIELD_FRAME_OFFSET 0
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#define CSI_PP_TOP_FIELD_FRAME_MASK_OFFSET 4
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#define TEGRA_CSI_PIXEL_STREAM_GAP 0x00c
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#define PP_FRAME_MIN_GAP_OFFSET 16
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#define TEGRA_CSI_PIXEL_STREAM_PP_COMMAND 0x010
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#define CSI_PP_ENABLE 0x1
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#define CSI_PP_DISABLE 0x2
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#define CSI_PP_RST 0x3
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#define CSI_PP_SINGLE_SHOT_ENABLE (0x1 << 2)
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#define CSI_PP_START_MARKER_FRAME_MAX_OFFSET 12
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#define TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME 0x014
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#define TEGRA_CSI_PIXEL_PARSER_INTERRUPT_MASK 0x018
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#define TEGRA_CSI_PIXEL_PARSER_STATUS 0x01c
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#define TEGRA_CSI_CSI_SW_SENSOR_RESET 0x020
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/* CSI PHY registers */
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/* CSI_PHY_CIL_COMMAND_0 offset 0x0d0 from TEGRA_CSI_PIXEL_PARSER_0_BASE */
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#define TEGRA_CSI_PHY_CIL_COMMAND 0x0d0
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#define CSI_A_PHY_CIL_NOP 0x0
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#define CSI_A_PHY_CIL_ENABLE 0x1
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#define CSI_A_PHY_CIL_DISABLE 0x2
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#define CSI_A_PHY_CIL_ENABLE_MASK 0x3
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#define CSI_B_PHY_CIL_NOP (0x0 << 8)
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#define CSI_B_PHY_CIL_ENABLE (0x1 << 8)
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#define CSI_B_PHY_CIL_DISABLE (0x2 << 8)
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#define CSI_B_PHY_CIL_ENABLE_MASK (0x3 << 8)
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/* CSI CIL registers: Starts from 0x92c, offset 0xF4 */
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#define TEGRA_CSI_CIL_OFFSET 0x0f4
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#define TEGRA_CSI_CIL_PAD_CONFIG0 0x000
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#define BRICK_CLOCK_A_4X (0x1 << 16)
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#define BRICK_CLOCK_B_4X (0x2 << 16)
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#define TEGRA_CSI_CIL_PAD_CONFIG1 0x004
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#define TEGRA_CSI_CIL_PHY_CONTROL 0x008
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#define BYPASS_LP_SEQ (0x1 << 6)
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#define TEGRA_CSI_CIL_INTERRUPT_MASK 0x00c
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#define TEGRA_CSI_CIL_STATUS 0x010
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#define TEGRA_CSI_CILX_STATUS 0x014
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#define TEGRA_CSI_CIL_ESCAPE_MODE_COMMAND 0x018
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#define TEGRA_CSI_CIL_ESCAPE_MODE_DATA 0x01c
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#define TEGRA_CSI_CIL_SW_SENSOR_RESET 0x020
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/* CSI Pattern Generator registers: Starts from 0x9c4, offset 0x18c */
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#define TEGRA_CSI_TPG_OFFSET 0x18c
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#define TEGRA_CSI_PATTERN_GENERATOR_CTRL 0x000
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#define PG_MODE_OFFSET 2
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#define PG_ENABLE 0x1
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#define PG_DISABLE 0x0
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#define PG_VBLANK_OFFSET 16
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#define TEGRA_CSI_PG_BLANK 0x004
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#define TEGRA_CSI_PG_PHASE 0x008
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#define TEGRA_CSI_PG_RED_FREQ 0x00c
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#define PG_RED_VERT_INIT_FREQ_OFFSET 16
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#define PG_RED_HOR_INIT_FREQ_OFFSET 0
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#define TEGRA_CSI_PG_RED_FREQ_RATE 0x010
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#define TEGRA_CSI_PG_GREEN_FREQ 0x014
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#define PG_GREEN_VERT_INIT_FREQ_OFFSET 16
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#define PG_GREEN_HOR_INIT_FREQ_OFFSET 0
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#define TEGRA_CSI_PG_GREEN_FREQ_RATE 0x018
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#define TEGRA_CSI_PG_BLUE_FREQ 0x01c
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#define PG_BLUE_VERT_INIT_FREQ_OFFSET 16
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#define PG_BLUE_HOR_INIT_FREQ_OFFSET 0
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#define TEGRA_CSI_PG_BLUE_FREQ_RATE 0x020
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#define TEGRA_CSI_PG_AOHDR 0x024
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#define TEGRA_CSI_DPCM_CTRL_A 0xa2c
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#define TEGRA_CSI_DPCM_CTRL_B 0xa30
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/* Other CSI registers: Starts from 0xa44, offset 0x20c */
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#define TEGRA_CSI_STALL_COUNTER 0x20c
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#define TEGRA_CSI_CSI_READONLY_STATUS 0x210
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#define TEGRA_CSI_CSI_SW_STATUS_RESET 0x214
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#define TEGRA_CSI_CLKEN_OVERRIDE 0x218
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#define TEGRA_CSI_DEBUG_CONTROL 0x21c
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#define TEGRA_CSI_DEBUG_COUNTER_0 0x220
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#define TEGRA_CSI_DEBUG_COUNTER_1 0x224
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#define TEGRA_CSI_DEBUG_COUNTER_2 0x228
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/* CSI Pixel Parser registers */
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#define TEGRA_CSI_PIXEL_PARSER_0_BASE 0x0838
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#define TEGRA_CSI_PIXEL_PARSER_1_BASE 0x086c
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#define TEGRA_CSI_PIXEL_PARSER_2_BASE 0x1038
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#define TEGRA_CSI_PIXEL_PARSER_3_BASE 0x106c
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#define TEGRA_CSI_PIXEL_PARSER_4_BASE 0x1838
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#define TEGRA_CSI_PIXEL_PARSER_5_BASE 0x186c
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/* CSIA to CSIB register offset */
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#define TEGRA_CSI_PORT_OFFSET 0x34
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#define INVALID_CSI_PORT 0xFF
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#define TEGRA_CSI_BLOCKS 3
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#define SYNCPT_FIFO_DEPTH 2
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#define PREVIOUS_BUFFER_DEC_INDEX 2
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#define TEGRA_CLOCK_VI_MAX 793600000
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#define TEGRA_CLOCK_TPG 927000000
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#define TEGRA_CLOCK_CSI_PORT_MAX 102000000
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#define TEGRA_SURFACE_ALIGNMENT 64
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#endif
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