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9764cf5370
- This change adds support for new IPC type DCE_IPC_TYPE_RM_NOTIFY wrt event notification from DCE RM JIRA TDS-6643 Change-Id: I54b22e3fa86a1dab552f78d609c374d14ce619ad Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2409904 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Santosh Galma <galmar@nvidia.com> Reviewed-by: Arun Swain <arswain@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Santosh Galma <galmar@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
114 lines
4.0 KiB
C
114 lines
4.0 KiB
C
/*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* NVIDIA Corporation and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA Corporation is strictly prohibited.
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*/
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#ifndef DCE_INTERFACE_H
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#define DCE_INTERFACE_H
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#include <interface/dce-bitops.h>
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/*
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* XXX: TODO
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*
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* These should be defined in terms of the HW registers
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*/
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#define DCE_NUM_SEMA_REGS 4
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#define DCE_NUM_MBOX_REGS 8
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/*
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* Symbolic definitions of the semaphore registers
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*/
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typedef uint32_t hsp_sema_t;
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#define DCE_BOOT_SEMA (hsp_sema_t)0U
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/*
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* Definitions for DCE_BOOT_SEMA
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*
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* Used to communicate bits of information between the OS and DCE
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*/
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/*
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* Bits set by the OS and examined by the R5
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*/
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#define DCE_BOOT_INT DCE_BIT(31) // interrupt when DCE is ready
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#define DCE_WAIT_DEBUG DCE_BIT(30) // wait in debug loop
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#define DCE_SC7_RESUME DCE_BIT(29) // resume using saved SC7 state
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// rather than a full restart
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#define DCE_OS_BITMASK (DCE_BOOT_INT | DCE_WAIT_DEBUG | DCE_SC7_RESUME)
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/*
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* Bits set by the R5 and examined by the OS
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*/
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#define DCE_BOOT_TCM_COPY DCE_BIT(15) // uCode has copied to TCM
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#define DCE_BOOT_HW_INIT DCE_BIT(14) // hardware init complete
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#define DCE_BOOT_MPU_INIT DCE_BIT(13) // MPU initialized
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#define DCE_BOOT_CACHE_INIT DCE_BIT(12) // cache initialized
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#define DCE_BOOT_R5_INIT DCE_BIT(11) // R5 initialized
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#define DCE_BOOT_DRIVER_INIT DCE_BIT(10) // driver init complete
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#define DCE_BOOT_MAIN_STARTED DCE_BIT(9) // main started
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#define DCE_BOOT_TASK_INIT_START DCE_BIT(8) // task initialization started
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#define DCE_BOOT_TASK_INIT_DONE DCE_BIT(7) // task initialization complete
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#define DCE_HALTED DCE_BIT(1) // uCode has halted
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#define DCE_BOOT_COMPLETE DCE_BIT(0) // uCode boot has completed
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/*
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* Symbolic definitions of the doorbell registers
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*/
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typedef uint32_t hsp_db_t;
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/*
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* Symbolic definitions of the mailbox registers (rather than using 0-7)
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*/
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typedef uint32_t hsp_mbox_t;
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#define DCE_MBOX_FROM_DCE_RM (hsp_mbox_t)0U // signal from RM IPC
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#define DCE_MBOX_TO_DCE_RM (hsp_mbox_t)1U // signal to RM IPC
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#define DCE_MBOX_FROM_DCE_RM_EVENT_NOTIFY (hsp_mbox_t)2U // signal to DCE for event notification
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#define DCE_MBOX_TO_DCE_RM_EVENT_NOTIFY (hsp_mbox_t)3U // signal from DCE for event notification IPC
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#define DCE_MBOX_FROM_DCE_ADMIN (hsp_mbox_t)4U // signal from DCE ADMIN IPC
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#define DCE_MBOX_TO_DCE_ADMIN (hsp_mbox_t)5U // signal to ADMIN IPC
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#define DCE_MBOX_BOOT_CMD (hsp_mbox_t)6U // boot commands
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#define DCE_MBOX_IRQ (hsp_mbox_t)7U // general interrupt/status
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/*
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* Generic interrupts & status from the DCE are reported in DCE_MBOX_IRQ
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*/
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#define DCE_IRQ_PENDING DCE_BIT(31)// interrupt is pending
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#define DCE_IRQ_GET_STATUS_TYPE(_x_) DCE_EXTRACT(_x_, 30, 27, uint32_t)
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#define DCE_IRQ_SET_STATUS_TYPE(_x_) DCE_INSERT(0U, 30, 27, _x_)
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#define DCE_IRQ_STATUS_TYPE_IRQ 0x0 // irq status
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#define DCE_IRQ_STATUS_TYPE_BOOT_CMD 0x1 // boot command status
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#define NUM_DCE_IRQ_STATUS_TYPES 2
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#define DCE_IRQ_GET_STATUS(_x_) DCE_EXTRACT(_x_, 23, 0, uint32_t)
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#define DCE_IRQ_SET_STATUS(_x_) DCE_INSERT(0U, 23, 0, _x_)
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/*
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* Bits in status field when IRQ_STATUS_TYPE == IRQ_STATUS_TYPE_IRQ
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*/
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#define DCE_IRQ_READY DCE_BIT(23) // DCE is ready
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#define DCE_IRQ_LOG_OVERFLOW DCE_BIT(22) // trace log overflow
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#define DCE_IRQ_LOG_READY DCE_BIT(21) // trace log buffers available
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#define DCE_IRQ_CRASH_LOG DCE_BIT(20) // crash log available
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#define DCE_IRQ_ABORT DCE_BIT(19) // uCode abort occurred
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#define DCE_IRQ_SC7_ENTERED DCE_BIT(18) // DCE state saved
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// can be powered off
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/*
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* MBOX contents for IPC are the same for all of the mailboxes that are
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* used for signaling IPC. Not all values will be useful for all mailboxes.
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*/
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#define DCE_IPC_IRQ_PENDING DCE_BIT(31) // interrupt is pending
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#endif
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