mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 09:11:26 +03:00
9a57665a0f
This change adds the support for programming streamids to allow tsec fw on t264 to access PA at a low privilege level. It also includes the synchronization logic to communicate with the fw regarding completion of stream id programming so that the fw can go ahead and initialize itself. In addition to this, the mailbox used for communicating init done from tsec fw to ccplex is changed from NV_PTSEC_FALCON_MAILBOX0 to NV_PTSEC_MAILBOX1 since CCPLEX does not have access to the former from t26x onwards. Hence falcon based mailboxes are used for tsec-psc comms and non-falcon ones for tsec-ccplex comms (stream id comms and init done). Jira TSEC-14 Change-Id: I2871a52222cd69786a8cc3f53162a80486611bb5 Signed-off-by: Sahil Patki <spatki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3366343 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> (cherry picked from commit db54fde9c4d786b22b7f8694753de3ec80649b17) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3400219
94 lines
1.9 KiB
C
94 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Tegra TSEC Module Support
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*/
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#ifndef TSEC_H
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#define TSEC_H
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#include "tsec_regs.h"
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/*
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* TSEC Device Data Structure
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*/
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#define TSEC_CLK_NAME "tsec"
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#define TSEC_CLK_INDEX (0)
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#define EFUSE_CLK_NAME "efuse"
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#define EFUSE_CLK_INDEX (1)
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#define TSEC_PKA_CLK_NAME "tsec_pka"
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#define TSEC_PKA_CLK_INDEX (2)
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#define TSEC_NUM_OF_CLKS (3)
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enum tsec_soc {
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TSEC_ON_T23x = 0,
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TSEC_ON_T239,
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TSEC_ON_T26x,
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TSEC_ON_INVALID,
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};
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struct tsec_device_data {
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void __iomem *reg_aperture;
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struct device_dma_parameters dma_parms;
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int irq;
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/* spin lock for module irq */
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spinlock_t mirq_lock;
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/* If module is powered on */
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bool power_on;
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struct clk *clk[TSEC_NUM_OF_CLKS];
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long rate[TSEC_NUM_OF_CLKS];
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/* private platform data */
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void *private_data;
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/* owner platform_device */
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struct platform_device *pdev;
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/* reset control for this device */
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struct reset_control *reset_control;
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/* store the risc-v info */
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void *riscv_data;
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/* name of riscv descriptor binary */
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char *riscv_desc_bin;
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/* name of riscv image binary */
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char *riscv_image_bin;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debug_root;
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#endif /* CONFIG_DEBUG_FS */
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/* Number of bits for DMA mask - IOVA/PA number of bits */
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u8 dma_mask_bits;
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/* Which SOC Tsec is running on */
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enum tsec_soc soc;
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/* store the register offsets */
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struct tsec_reg_offsets_t *tsec_reg_offsets;
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};
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/*
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* TSEC Register Access APIs
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*/
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void tsec_writel(struct tsec_device_data *pdata, u32 r, u32 v);
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u32 tsec_readl(struct tsec_device_data *pdata, u32 r);
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/*
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* TSEC power on/off APIs
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*/
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int tsec_poweron(struct device *dev);
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int tsec_poweroff(struct device *dev);
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/*
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* TSEC StreamID Register Programming Operation
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*/
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void tsec_set_streamid_regs(struct device *dev,
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struct tsec_device_data *pdata);
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#endif /* TSEC_H */
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