mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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9a57665a0f
This change adds the support for programming streamids to allow tsec fw on t264 to access PA at a low privilege level. It also includes the synchronization logic to communicate with the fw regarding completion of stream id programming so that the fw can go ahead and initialize itself. In addition to this, the mailbox used for communicating init done from tsec fw to ccplex is changed from NV_PTSEC_FALCON_MAILBOX0 to NV_PTSEC_MAILBOX1 since CCPLEX does not have access to the former from t26x onwards. Hence falcon based mailboxes are used for tsec-psc comms and non-falcon ones for tsec-ccplex comms (stream id comms and init done). Jira TSEC-14 Change-Id: I2871a52222cd69786a8cc3f53162a80486611bb5 Signed-off-by: Sahil Patki <spatki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3366343 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> (cherry picked from commit db54fde9c4d786b22b7f8694753de3ec80649b17) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3400219
91 lines
2.2 KiB
C
91 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Tegra TSEC Module Support
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*/
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#ifndef TSEC_BOOT_H
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#define TSEC_BOOT_H
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#define RISCV_IDLE_TIMEOUT_DEFAULT 100000 /* 100 milliseconds */
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#define RISCV_IDLE_TIMEOUT_LONG 2000000 /* 2 seconds */
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#define RISCV_IDLE_CHECK_PERIOD 10 /* 10 usec */
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#define RISCV_IDLE_CHECK_PERIOD_LONG 1000 /* 1 milliseconds */
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/* TSEC RISCV boot status values */
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#define TSEC_RISCV_INIT_SUCCESS (0xa5a5a5a5)
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#define TSEC_RISCV_SMMU_STREAMID1 BIT_ULL(40)
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#define TSEC_RISCV_STREAMID_SET_DONE (0xa6a6a6a6)
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/* Image descriptor format */
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struct RM_RISCV_UCODE_DESC {
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/*
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* Version 1
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* Version 2
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* Vesrion 3 = for Partition boot
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* Vesrion 4 = for eb riscv boot
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*/
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u32 version; /* structure version */
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u32 bootloaderOffset;
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u32 bootloaderSize;
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u32 bootloaderParamOffset;
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u32 bootloaderParamSize;
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u32 riscvElfOffset;
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u32 riscvElfSize;
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u32 appVersion; /* Changelist number associated with the image */
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/*
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* Manifest contains information about Monitor and it is
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* input to BR
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*/
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u32 manifestOffset;
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u32 manifestSize;
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/*
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* Monitor Data offset within RISCV image and size
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*/
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u32 monitorDataOffset;
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u32 monitorDataSize;
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/*
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* Monitor Code offset withtin RISCV image and size
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*/
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u32 monitorCodeOffset;
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u32 monitorCodeSize;
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u32 bIsMonitorEnabled;
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/*
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* Swbrom Code offset within RISCV image and size
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*/
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u32 swbromCodeOffset;
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u32 swbromCodeSize;
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/*
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* Swbrom Data offset within RISCV image and size
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*/
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u32 swbromDataOffset;
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u32 swbromDataSize;
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};
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struct riscv_image_desc {
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u32 manifest_offset;
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u32 manifest_size;
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u32 data_offset;
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u32 data_size;
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u32 code_offset;
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u32 code_size;
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};
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struct riscv_data {
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bool valid;
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struct riscv_image_desc desc;
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dma_addr_t backdoor_img_iova;
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u32 *backdoor_img_va;
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size_t backdoor_img_size;
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bool ipc_mem_initialised;
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void __iomem *ipc_co_va;
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dma_addr_t ipc_co_iova;
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};
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int tsec_kickoff_boot(struct platform_device *pdev);
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int tsec_finalize_poweron(struct platform_device *dev);
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int tsec_prepare_poweroff(struct platform_device *dev);
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#endif /* TSEC_BOOT_H */
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