mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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9a57665a0f
This change adds the support for programming streamids to allow tsec fw on t264 to access PA at a low privilege level. It also includes the synchronization logic to communicate with the fw regarding completion of stream id programming so that the fw can go ahead and initialize itself. In addition to this, the mailbox used for communicating init done from tsec fw to ccplex is changed from NV_PTSEC_FALCON_MAILBOX0 to NV_PTSEC_MAILBOX1 since CCPLEX does not have access to the former from t26x onwards. Hence falcon based mailboxes are used for tsec-psc comms and non-falcon ones for tsec-ccplex comms (stream id comms and init done). Jira TSEC-14 Change-Id: I2871a52222cd69786a8cc3f53162a80486611bb5 Signed-off-by: Sahil Patki <spatki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3366343 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> (cherry picked from commit db54fde9c4d786b22b7f8694753de3ec80649b17) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3400219
130 lines
3.6 KiB
C
130 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Tegra TSEC Module Support
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*/
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/*
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* Function naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_o(void) : Returns the offset for element <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef TSEC_REGS_H
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#define TSEC_REGS_H
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#include <linux/types.h>
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struct tsec_reg_offsets_t {
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u32 QUEUE_HEAD_0;
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u32 QUEUE_TAIL_0;
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u32 MSGQ_HEAD_0;
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u32 MSGQ_TAIL_0;
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u32 EMEMC_0;
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u32 EMEMD_0;
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u32 THI_INT_STATUS_0;
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u32 THI_INT_STATUS_CLR_0;
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u32 THI_STREAMID0_0;
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u32 THI_STREAMID1_0;
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u32 PRIV_BLOCKER_CTRL_CG1;
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u32 RISCV_CG;
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u32 RISCV_IRQSCLR_0;
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u32 RISCV_IRQSTAT_0;
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u32 RISCV_IRQMSET_0;
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u32 RISCV_IRQMCLR_0;
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u32 RISCV_IRQSCLR_SWGEN0_SET;
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u32 RISCV_IRQMCLR_SWGEN0_SET;
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u32 RISCV_IRQMCLR_SWGEN1_SET;
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u32 RISCV_IRQSTAT_SWGEN0;
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u32 RISCV_IRQSTAT_SWGEN1;
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u32 RISCV_IRQMSET_SWGEN0_SET;
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u32 THI_SEC_0;
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u32 THI_SEC_CHLOCK;
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u32 RISCV_BCR_CTRL;
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u32 RISCV_BCR_CTRL_CORE_SELECT_RISCV;
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u32 RISCV_BCR_DMAADDR_PKCPARAM_LO;
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u32 RISCV_BCR_DMAADDR_PKCPARAM_HI;
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u32 RISCV_BCR_DMAADDR_FMCCODE_LO;
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u32 RISCV_BCR_DMAADDR_FMCCODE_HI;
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u32 RISCV_BCR_DMAADDR_FMCDATA_LO;
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u32 RISCV_BCR_DMAADDR_FMCDATA_HI;
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u32 RISCV_BCR_DMACFG;
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u32 RISCV_BCR_DMACFG_TARGET_LOCAL_FB;
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u32 RISCV_BCR_DMACFG_LOCK_LOCKED;
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u32 RISCV_BCR_DMACFG_SEC;
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u32 RISCV_BCR_DMACFG_SEC_GSCID;
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u32 FALCON_MAILBOX0;
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u32 FALCON_MAILBOX1;
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u32 MAILBOX0;
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u32 MAILBOX1;
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u32 RISCV_CPUCTL;
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u32 RISCV_CPUCTL_STARTCPU_TRUE;
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u32 RISCV_CPUCTL_ACTIVE_STAT;
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u32 RISCV_CPUCTL_ACTIVE_STAT_ACTIVE;
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u32 RISCV_BR_RETCODE;
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u32 RISCV_BR_RETCODE_RESULT;
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u32 RISCV_BR_RETCODE_RESULT_PASS;
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u32 FALCON_DMEMC_0;
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u32 FALCON_DMEMD_0;
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u32 DMEM_LOGBUF_OFFSET;
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};
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static inline u32 tsec_riscv_bcr_dmacfg_sec_gscid_f(u32 v, u32 offset)
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{
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return ((v & offset) << 16);
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}
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static inline u32 tsec_riscv_cpuctl_active_stat_v(u32 r, u32 offset)
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{
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return ((r >> offset) & 0x1);
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}
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static inline u32 tsec_riscv_br_retcode_result_v(u32 r, u32 offset)
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{
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return ((r >> offset) & 0x3);
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}
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static inline u32 tsec_falcon_dmemc_r(u32 r, u32 offset)
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{
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return (offset + (r) * 8);
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}
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static inline u32 tsec_falcon_dmemd_r(u32 r, u32 offset)
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{
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return (offset + (r) * 8);
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}
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#endif /* TSEC_REGS_H */
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