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748fa9c699
- Renamed the directory to oak - Updated the make files to compile the source - Removed unused script ESDP-16549 Bug 3882239 Bug 3824037 Change-Id: I1dee5def85b6e25f88dff999f1051bfe62d5613b Signed-off-by: Sheetal Tigadoli <stigadoli@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2856988 Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
72 lines
3.0 KiB
C
72 lines
3.0 KiB
C
/*
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*
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* If you received this File from Marvell, you may opt to use, redistribute and/or
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* modify this File in accordance with the terms and conditions of the General
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* Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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* available along with the File in the license.txt file or by writing to the Free
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* Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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* on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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* DISCLAIMED. The GPL License provides additional details about this warranty
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* disclaimer.
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*
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*/
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#ifndef H_OAK_GICU
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#define H_OAK_GICU
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/* Include for relation to classifier ldg_t */
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#include "ldg_t.h"
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typedef struct oak_gicustruct {
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#define OAK_GICU_IRQ_BASE 0x00070000U
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#define OAK_GICU_IRQ_REG(o) (OAK_GICU_IRQ_BASE + (o))
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#define TX_DMA_BIT 0
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#define TX_ERR_BIT 1
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#define RX_DMA_BIT 2
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#define RX_ERR_BIT 3
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#define UNIMAC_DMA_BIT 31
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#define OAK_GICU_INTR_DBG_CTRL OAK_GICU_IRQ_REG(0x000)
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#define OAK_GICU_INTR_FLAG_0 OAK_GICU_IRQ_REG(0x010)
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#define OAK_GICU_INTR_FLAG_1 OAK_GICU_IRQ_REG(0x014)
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#define OAK_GICU_HOST_SET_MASK_0 OAK_GICU_IRQ_REG(0x020)
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#define OAK_GICU_HOST_SET_MASK_1 OAK_GICU_IRQ_REG(0x024)
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#define OAK_GICU_HOST_CLR_MASK_0 OAK_GICU_IRQ_REG(0x030)
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#define OAK_GICU_HOST_CLR_MASK_1 OAK_GICU_IRQ_REG(0x034)
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#define OAK_GICU_HOST_MASK_0 0xFFFFFFFFU
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#define OAK_GICU_HOST_MASK_1 0x000000FFU
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#define OAK_GICU_HOST_MASK_E 0x003FFC00U
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#define OAK_GICU_HOST_UNIMAC_P11_IRQ BIT(8)
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#define OAK_GICU_HOST_UNIMAC_P11_RESET BIT(9)
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#define OAK_GICU_DBG_INTR_EVNT_0 OAK_GICU_IRQ_REG(0x040)
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#define OAK_GICU_DBG_INTR_EVNT_1 OAK_GICU_IRQ_REG(0x044)
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#define OAK_GICU_DBG_REG_0_L OAK_GICU_IRQ_REG(0x050)
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#define OAK_GICU_DBG_REG_0_H OAK_GICU_IRQ_REG(0x054)
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#define OAK_GICU_DBG_REG_1_L OAK_GICU_IRQ_REG(0x060)
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#define OAK_GICU_DBG_REG_1_H OAK_GICU_IRQ_REG(0x064)
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#define OAK_GICU_DBG_REG_2 OAK_GICU_IRQ_REG(0x070)
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#define OAK_GICU_DBG_REG_3 OAK_GICU_IRQ_REG(0x078)
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#define OAK_GICU_INTR_GRP_SET_MASK OAK_GICU_IRQ_REG(0x080)
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#define OAK_GICU_INTR_GRP_CLR_MASK OAK_GICU_IRQ_REG(0x084)
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#define OAK_GICU_INTR_GRP_MASK_ENABLE BIT(31)
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#define OAK_GICU_INTR_GRP_MASK_0 OAK_GICU_IRQ_REG(0x090)
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#define OAK_GICU_INTR_GRP_MASK_1 OAK_GICU_IRQ_REG(0x094)
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#define OAK_GICU_EPU_INTR_MASK_0 OAK_GICU_IRQ_REG(0x0C0)
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#define OAK_GICU_EPU_INTR_MASK_1 OAK_GICU_IRQ_REG(0x0C4)
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#define OAK_GICU_PIN_INTR_MASK_0 OAK_GICU_IRQ_REG(0x0d0)
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#define OAK_GICU_PIN_INTR_MASK_1 OAK_GICU_IRQ_REG(0x0d4)
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#define OAK_MAX_INTR_GRP 64
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#define OAK_MAX_CHAN_NUM 10
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#define OAK_GICU_INTR_GRP(g) OAK_GICU_IRQ_REG(0x100 + 4 * (g))
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#define OAK_INTR_MASK_TX_DMA BIT(0)
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#define OAK_INTR_MASK_TX_ERR BIT(1)
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#define OAK_INTR_MASK_RX_DMA BIT(2)
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#define OAK_INTR_MASK_RX_ERR BIT(3)
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#define OAK_NUM_IVEC (OAK_MAX_CHAN_NUM * 4 + 1)
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struct msix_entry msi_vec[OAK_NUM_IVEC];
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u32 num_ldg;
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ldg_t ldg[OAK_NUM_IVEC];
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} oak_gicu;
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#endif /* #ifndef H_OAK_GICU */
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