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git://nv-tegra.nvidia.com/linux-nv-oot.git
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77a7ea2c88
It may be useful at times to boot ADSP via backdoor, even while system boots via front door. MB2 sets the ACAST in front door, so ACAST setting from nvadsp driver is skipped if that region is already enabled. Above scheme will work for ADSP backdoor boot via SMMU mapped memory, but not for physical memory, as the underlying carveout memory is different between frontdoor and backdoor. Bug 200745826 Change-Id: I718da97e3f06eb86b3e40efab91275f2d5958dd4 Signed-off-by: Viswanath L <viswanathl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2675786 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Dara Ramesh <dramesh@nvidia.com> GVS: Gerrit_Virtual_Submit
241 lines
6.9 KiB
C
241 lines
6.9 KiB
C
/*
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* Copyright (C) 2016-2022 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/io.h>
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#include "dev.h"
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#include "dev-t18x.h"
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#define AST_CONTROL 0x000
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#define AST_STREAMID_CTL_0 0x020
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#define AST_STREAMID_CTL_1 0x024
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#define AST_RGN_SLAVE_BASE_LO 0x100
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#define AST_RGN_SLAVE_BASE_HI 0x104
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#define AST_RGN_MASK_BASE_LO 0x108
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#define AST_RGN_MASK_BASE_HI 0x10c
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#define AST_RGN_MASTER_BASE_LO 0x110
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#define AST_RGN_MASTER_BASE_HI 0x114
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#define AST_RGN_CONTROL 0x118
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#define AST_PAGE_MASK (~0xFFF)
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#define AST_LO_SHIFT 32
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#define AST_LO_MASK 0xFFFFFFFF
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#define AST_PHY_SID_IDX 0
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#define AST_APE_SID_IDX 1
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#define AST_NS (1 << 3)
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#define AST_CARVEOUTID(ID) (ID << 5)
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#define AST_VMINDEX(IDX) (IDX << 15)
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#define AST_PHSICAL(PHY) (PHY << 19)
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#define AST_STREAMID(ID) (ID << 8)
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#define AST_VMINDEX_ENABLE (1 << 0)
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#define AST_RGN_ENABLE (1 << 0)
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#define AST_RGN_OFFSET 0x20
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struct acast_region {
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u32 rgn;
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u32 rgn_ctrl;
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u32 strmid_reg;
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u32 strmid_ctrl;
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u64 slave;
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u64 size;
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u64 master;
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};
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#define NUM_MAX_ACAST 2
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#define ACAST_RGN_PHY 0x0
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#define ACAST_RGN_CTL_PHY (AST_PHSICAL(1) | AST_CARVEOUTID(0x7))
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#define ACAST_RGN_VM 0x2
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#define ACAST_VMINDEX 1
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#define ACAST_RGN_CTL_VM(IDX) AST_VMINDEX(IDX)
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#define ACAST_SID_REG_EVAL(IDX) AST_STREAMID_CTL_##IDX
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#define ACAST_STRMID_REG(IDX) ACAST_SID_REG_EVAL(IDX)
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#if KERNEL_VERSION(4, 14, 0) > LINUX_VERSION_CODE
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/* Older kernels do not have this function, so stubbing it */
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static inline int of_property_read_u64_index(const struct device_node *np,
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const char *propname, u32 index, u64 *out_value)
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{
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return -ENOSYS;
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}
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#endif
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static inline void acast_write(void __iomem *acast, u32 reg, u32 val)
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{
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writel(val, acast + reg);
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}
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static inline u32 acast_read(void __iomem *acast, u32 reg)
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{
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return readl(acast + reg);
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}
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static inline u32 acast_rgn_reg(u32 rgn, u32 reg)
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{
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return rgn * AST_RGN_OFFSET + reg;
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}
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static void tegra18x_acast_map(struct device *dev,
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void __iomem *acast, u32 rgn, u32 rgn_ctrl,
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u32 strmid_reg, u32 strmid_ctrl,
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u64 slave, u64 size, u64 master)
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{
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u32 val;
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val = acast_read(acast, acast_rgn_reg(rgn, AST_RGN_SLAVE_BASE_LO));
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if (val & AST_RGN_ENABLE) {
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dev_warn(dev, "ACAST rgn %u already mapped...skipping\n", rgn);
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return;
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}
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val = master & AST_LO_MASK;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_MASTER_BASE_LO), val);
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val = master >> AST_LO_SHIFT;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_MASTER_BASE_HI), val);
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val = ((size - 1) & AST_PAGE_MASK) & AST_LO_MASK;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_MASK_BASE_LO), val);
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val = (size - 1) >> AST_LO_SHIFT;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_MASK_BASE_HI), val);
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val = acast_read(acast, acast_rgn_reg(rgn, AST_RGN_CONTROL));
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val |= rgn_ctrl;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_CONTROL), val);
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if (strmid_reg)
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acast_write(acast, strmid_reg, strmid_ctrl);
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val = slave >> AST_LO_SHIFT;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_SLAVE_BASE_HI), val);
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val = (slave & AST_LO_MASK) | AST_RGN_ENABLE;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_SLAVE_BASE_LO), val);
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}
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static int tegra18x_acast_init(struct device *dev,
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uint32_t acast_addr, uint32_t acast_size,
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struct acast_region *acast_regions, uint32_t num_regions)
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{
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void __iomem *acast_base;
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int i;
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acast_base = devm_ioremap(dev, acast_addr, acast_size);
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if (IS_ERR_OR_NULL(acast_base)) {
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dev_err(dev, "failed to map ACAST 0x%x\n", acast_addr);
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return PTR_ERR(acast_base);
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}
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for (i = 0; i < num_regions; i++) {
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tegra18x_acast_map(dev, acast_base,
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acast_regions[i].rgn,
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acast_regions[i].rgn_ctrl,
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acast_regions[i].strmid_reg,
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acast_regions[i].strmid_ctrl,
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acast_regions[i].slave,
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acast_regions[i].size,
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acast_regions[i].master);
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dev_dbg(dev, "i:%d rgn:0x%x rgn_ctrl:0x%x ",
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i, acast_regions[i].rgn, acast_regions[i].rgn_ctrl);
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dev_dbg(dev, "strmid_reg:0x%x strmid_ctrl:0x%x ",
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acast_regions[i].strmid_reg,
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acast_regions[i].strmid_ctrl);
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dev_dbg(dev, "slave:0x%llx size:0x%llx master:0x%llx\n",
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acast_regions[i].slave, acast_regions[i].size,
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acast_regions[i].master);
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}
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return 0;
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}
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int nvadsp_acast_t18x_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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struct resource *co_mem = &drv_data->co_mem;
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uint32_t acast_addr, acast_size;
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int iter, num_acast = 0, ret = 0;
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struct acast_region acast_config;
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if (co_mem->start) {
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acast_config.rgn = ACAST_RGN_PHY;
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acast_config.rgn_ctrl = ACAST_RGN_CTL_PHY;
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acast_config.strmid_reg = 0;
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acast_config.strmid_ctrl = 0;
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acast_config.slave = drv_data->adsp_mem[ADSP_OS_ADDR];
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acast_config.size = drv_data->adsp_mem[ADSP_OS_SIZE];
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acast_config.master = co_mem->start;
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} else {
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uint32_t stream_id;
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uint64_t iommu_addr_start, iommu_addr_end;
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if (of_property_read_u32_index(dev->of_node,
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"iommus", 1, &stream_id)) {
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dev_warn(dev, "no SMMU stream ID found\n");
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goto exit;
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}
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if (of_property_read_u64_index(dev->of_node,
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"iommu-resv-regions", 1, &iommu_addr_start)) {
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dev_warn(dev, "no IOMMU reserved region\n");
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goto exit;
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}
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if (of_property_read_u64_index(dev->of_node,
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"iommu-resv-regions", 2, &iommu_addr_end)) {
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dev_warn(dev, "no IOMMU reserved region\n");
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goto exit;
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}
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acast_config.rgn = ACAST_RGN_VM;
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acast_config.rgn_ctrl = ACAST_RGN_CTL_VM(ACAST_VMINDEX);
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acast_config.strmid_reg = ACAST_STRMID_REG(ACAST_VMINDEX);
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acast_config.strmid_ctrl = AST_STREAMID(stream_id) |
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AST_VMINDEX_ENABLE;
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acast_config.slave = iommu_addr_start;
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acast_config.size = (iommu_addr_end - acast_config.slave);
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acast_config.master = iommu_addr_start;
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}
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for (iter = 0; iter < (NUM_MAX_ACAST * 2); iter += 2) {
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if (of_property_read_u32_index(dev->of_node,
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"nvidia,acast_config", iter, &acast_addr))
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continue;
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if (of_property_read_u32_index(dev->of_node,
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"nvidia,acast_config", (iter + 1), &acast_size))
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continue;
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ret = tegra18x_acast_init(dev, acast_addr, acast_size,
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&acast_config, 1);
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if (ret)
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goto exit;
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num_acast++;
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}
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if (num_acast == 0)
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dev_warn(dev, "no ACAST configurations found\n");
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exit:
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return ret;
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}
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