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git://nv-tegra.nvidia.com/linux-nv-oot.git
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e6e4bbc853
Combined nvaudio-ivc with tegra-virt-alt. Bug 3735757 Change-Id: I9642c5367e43bfc470c70641fa22e50a4ae0e992 Signed-off-by: pmedawala <pmedawala@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2800354 GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Reviewed-by: Uday Gupta <udayg@nvidia.com> Reviewed-by: Niranjan Dighe <ndighe@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
61 lines
1.5 KiB
C
61 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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#ifndef __TEGRA_ASOC_UTILS_ALT_H_
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#define __TEGRA_ASOC_UTILS_ALT_H_
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struct clk;
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struct device;
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enum tegra_asoc_utils_soc {
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TEGRA_ASOC_UTILS_SOC_TEGRA210,
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TEGRA_ASOC_UTILS_SOC_TEGRA186,
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TEGRA_ASOC_UTILS_SOC_TEGRA194,
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};
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/*
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* Maintain same order in DT entry
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* FIXME: (This would be removed going ahead)
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*/
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enum tegra_asoc_utils_clkrate {
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PLLA_x11025_RATE,
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AUD_MCLK_x11025_RATE,
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PLLA_OUT0_x11025_RATE,
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AHUB_x11025_RATE,
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PLLA_x8000_RATE,
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AUD_MCLK_x8000_RATE,
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PLLA_OUT0_x8000_RATE,
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AHUB_x8000_RATE,
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MAX_NUM_RATES,
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};
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struct tegra_asoc_audio_clock_info {
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struct device *dev;
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struct snd_soc_card *card;
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enum tegra_asoc_utils_soc soc;
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struct clk *clk_pll_base;
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struct clk *clk_pll_out;
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struct clk *clk_aud_mclk;
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struct reset_control *clk_cdev1_rst;
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unsigned int *pll_base_rate;
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u32 set_pll_base_rate;
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u32 set_pll_out_rate;
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u32 set_aud_mclk_rate;
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u32 mclk_scale;
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/* FIXME: below would be removed going ahead */
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u32 clk_rates[MAX_NUM_RATES];
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u32 num_clk;
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};
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int tegra_alt_asoc_utils_set_rate(struct tegra_asoc_audio_clock_info *data,
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unsigned int srate, unsigned int mclk,
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unsigned int clk_out_rate);
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int tegra_alt_asoc_utils_init(struct tegra_asoc_audio_clock_info *data,
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struct device *dev, struct snd_soc_card *card);
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int tegra_alt_asoc_utils_clk_enable(struct tegra_asoc_audio_clock_info *data);
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int tegra_alt_asoc_utils_clk_disable(struct tegra_asoc_audio_clock_info *data);
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#endif |