mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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2e68d82f52
Move files from private-soc to parent controller directory. Bug 5054840 Change-Id: I8ec5e5b34f2226bbbd051f4313033153a096e5c1 Signed-off-by: Prakhar Srivastava <prasrivastav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3312461 Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
186 lines
5.1 KiB
C
186 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved */
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/* No header guards as this file doesnot define any. Added for documentation only */
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/**
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* @defgroup CalPcieEpLinux PCIe_EP_Linux_Device_Tree
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*
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* **PCIe Controller DT properties**
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*
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* `compatible`:
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*
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* - **Description:** Compatibility string name.
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*
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* - **Range:** "nvidia,tegra264-pcie-ep".
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*
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* - **Resolution:**:
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*
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* * Customizable: No.
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*
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* * Optional: No.
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*
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* `status`:
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*
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* - **Description:** Enabled status of PCIe controller.
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*
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* - **Range:** "okay" or "disabled"
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*
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* - **Resolution:**
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*
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* - Customizable: No.
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*
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* * Optional: No.
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*
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* `reg`:
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*
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* - **Description:** A list of physical base address and length pairs for each set of controller
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* registers. Must contain an entry for each entry in the reg-names property in same order.
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*
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* - **Range:** Values for EP Controller (C2, C4, C5) respectively are
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*
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reg = <0xa8 0x08420000 0x0 0x00004000
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0xa8 0x08500000 0x0 0x00001000
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0xa8 0x08510000 0x0 0x00001000
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0xa8 0x08511000 0x0 0x00001000
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0xa8 0x08520000 0x0 0x00010000
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0xa8 0x08430000 0x0 0x00010000
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0xb0 0x80000000 0x8 0x00000000>;
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reg = <0xa8 0x08460000 0x0 0x00004000
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0xa8 0x08530000 0x0 0x00001000
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0xa8 0x08540000 0x0 0x00001000
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0xa8 0x08541000 0x0 0x00001000
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0xa8 0x08550000 0x0 0x00010000
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0xa8 0x08470000 0x0 0x00010000
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0xc0 0x80000000 0x8 0x00000000>;
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reg = <0xa8 0x08480000 0x0 0x00004000
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0xa8 0x08560000 0x0 0x00001000
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0xa8 0x08570000 0x0 0x00001000
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0xa8 0x08571000 0x0 0x00001000
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0xa8 0x08580000 0x0 0x00010000
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0xa8 0x08490000 0x0 0x00010000
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0xc8 0x80000000 0x8 0x00000000>;
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* - **Resolution:**:
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*
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* * Customizable: No.
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*
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* * Optional: No.
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*
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* `reg-names`:
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*
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* - **Description:** Names of the registers defined in `reg` property. Details explained in the
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* range.
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*
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* - **Range:** Must include the following entries in same order:
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* - xal: Controller's application logic registers.
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* - xal-ep-dm: Controller's transport layer
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* - xtl-ep-pri: Controller's transport layer private registers.
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* - xtl-ep-cfg: Controller's PCIe config registers.
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* - xpl: Controller's physical layer registers.
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* - xdma: Controller's XDMA registers.
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* - addr_space: Used to map remote RC address space
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*
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* - **Resolution:**:
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*
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* * Customizable: No.
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*
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* * Optional: No.
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*
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* `intr`:
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*
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* - **Description:** A list of interrupt outputs of the controller. Must contain an entry for
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* each entry in the interrupt-names property
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*
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* - **Range:** Values for EP Controller (C2, C4, C5) are 0x391, 0x3a4 and 0x3ad respectively.
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*
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* - **Resolution:**:
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*
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* * Customizable: No.
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*
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* * Optional: No.
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*
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* `intr-names`:
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*
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* - **Description:** Names of the registers defined in `intr` property. Details explained in the
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* range.
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*
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* - **Range:** Must include the "intr" entry
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*
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* - **Resolution:**:
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*
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* * Customizable: No.
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*
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* * Optional: No.
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*
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* `nvidia,bpmp`:
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*
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* - **Description:** Contains phanldle of bpmp node and controller ID of the PCIe controller.
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*
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* - **Range:** Supported values for controller ID are 2, 4, 5.
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*
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* - **Resolution:**:
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*
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* * Customizable: No.
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*
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* * Optional: No.
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*
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* `dma-coherent`:
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*
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* - **Description:** boolean flag which indicates whether PCIe is DMA coherent or not.
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*
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* - **Resolution:**:
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*
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* * Customizable: No.
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*
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* * Optional: No.
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*
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* `reset-gpios`:
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*
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* - **Description:** Must contain a phandle to a GPIO controller followed by GPIO that is being
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* used as PERST input signal.
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*
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* - **Resolution:**:
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*
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* * Customizable: Yes, based on the platform design.
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*
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* * Optional: No.
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*
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* `nvidia,pex-prsnt-gpios`:
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*
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* - **Description:** Must contain a phandle to a GPIO controller followed by GPIO that is being
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* used as PRSNT output signal.
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* This GPIO is used to generate hot-plug events to the connected root port device.
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*
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* - **Resolution:**:
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*
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* * Customizable: Yes, based on the platform design.
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*
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* * Optional: Yes.
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*
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* Example:
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@verbatim
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pcie-ep@a808460000 {
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status = "disabled";
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compatible = "nvidia,tegra264-pcie-ep";
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reg = <0xa8 0x08460000 0x0 0x00004000
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0xa8 0x08530000 0x0 0x00001000
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0xa8 0x08540000 0x0 0x00001000
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0xa8 0x08541000 0x0 0x00001000
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0xa8 0x08550000 0x0 0x00010000
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0xa8 0x08470000 0x0 0x00010000
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0xc0 0x80000000 0x8 0x00000000>;
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reg-names = "xal", "xal-ep-dm", "xtl-ep-pri", "xtl-ep-cfg", "xdma", "xpl", "addr_space";
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interrupts = <GIC_SPI 0x3a4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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reset-gpios = <&gpio_uphy TEGRA264_UPHY_GPIO(D, 1) GPIO_ACTIVE_LOW>;
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iommus = <&smmu1_mmu 0x40000>;
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dma-coherent;
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msi-parent = <&its 0x140000>;
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nvidia,bpmp = <&bpmp 0x4>;
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};
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@endverbatim
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*/
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