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git://nv-tegra.nvidia.com/linux-nv-oot.git
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a0deb314ae
Some of the AHUB module drivers have soc_data information only to define a function pointer for calling tegra210_xbar_set_cif(). This function is implemented in xbar utils driver and exported. This patch removes function pointer reference to above and instead make calls directly. This helps to cleanup soc_data for all modules and further for few modules soc_data is completely removed. Bug 200503387 Change-Id: If919e5f7a7a92351940bf46f7302fd40c76c7ea3 Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2140228 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mohan Kumar D <mkumard@nvidia.com> Reviewed-by: Dara Ramesh <dramesh@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sharad Gupta <sharadg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
143 lines
5.1 KiB
C
143 lines
5.1 KiB
C
/*
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* tegra210_dmic_alt.h - Definitions for Tegra210 DMIC driver
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*
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* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA210_DMIC_ALT_H__
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#define __TEGRA210_DMIC_ALT_H__
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/* Register offsets from DMIC BASE */
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#define TEGRA210_DMIC_TX_STATUS 0x0c
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#define TEGRA210_DMIC_TX_INT_STATUS 0x10
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#define TEGRA210_DMIC_TX_INT_MASK 0x14
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#define TEGRA210_DMIC_TX_INT_SET 0x18
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#define TEGRA210_DMIC_TX_INT_CLEAR 0x1c
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#define TEGRA210_DMIC_TX_CIF_CTRL 0x20
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#define TEGRA210_DMIC_ENABLE 0x40
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#define TEGRA210_DMIC_SOFT_RESET 0x44
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#define TEGRA210_DMIC_CG 0x48
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#define TEGRA210_DMIC_STATUS 0x4c
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#define TEGRA210_DMIC_INT_STATUS 0x50
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#define TEGRA210_DMIC_CTRL 0x64
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#define TEGRA210_DMIC_DBG_CTRL 0x70
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#define TEGRA210_DMIC_DCR_FILTER_GAIN 0x74
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#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_0 0x78
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#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_1 0x7c
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#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_2 0x80
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#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_3 0x84
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#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4 0x88
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#define TEGRA210_DMIC_LP_FILTER_GAIN 0x8c
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#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_0 0x90
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#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_1 0x94
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#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_2 0x98
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#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_3 0x9c
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#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_4 0xa0
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#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_0 0xa4
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#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_1 0xa8
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#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_2 0xac
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#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_3 0xb0
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#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_4 0xb4
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#define TEGRA210_DMIC_CORRECTION_FILTER_GAIN 0xb8
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#define TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_0 0xbc
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#define TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_1 0xc0
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#define TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_2 0xc4
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#define TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_3 0xc8
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#define TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_4 0xcc
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#define TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_0 0xd0
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#define TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_1 0xd4
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#define TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_2 0xd8
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#define TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_3 0xdc
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#define TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_4 0xe0
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/* Constants for DMIC */
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#define TEGRA210_DMIC_OSR_64 0
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#define TEGRA210_DMIC_OSR_128 1
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#define TEGRA210_DMIC_OSR_256 2
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/* Fields in TEGRA210_DMIC_ENABLE */
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#define TEGRA210_DMIC_ENABLE_EN_SHIFT 0
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#define TEGRA210_DMIC_ENABLE_EN BIT(0)
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/* Fields in TEGRA210_DMIC_SOFT_RESET */
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#define TEGRA210_DMIC_SOFT_RESET_EN BIT(0)
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/* Fields in TEGRA210_DMIC_CG */
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#define TEGRA210_DMIC_CG_SLCG_EN BIT(0)
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/* Fields in TEGRA210_DMIC_STATUS */
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#define TEGRA210_DMIC_STATUS_CONFIG_ERROR_SHIFT 31
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#define TEGRA210_DMIC_STATUS_CONFIG_ERROR_MASK (0x1 << TEGRA210_DMIC_STATUS_CONFIG_ERROR_SHIFT)
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#define TEGRA210_DMIC_STATUS_SLCG_CLKEN_SHIFT 8
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#define TEGRA210_DMIC_STATUS_SLCG_CLKEN_MASK (0x1 << TEGRA210_DMIC_STATUS_SLCG_CLKEN_SHIFT)
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#define TEGRA210_DMIC_STATUS_ENABLE_STATUS_SHIFT 0
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#define TEGRA210_DMIC_STATUS_ENABLE_STATUS_MASK (0x1 << TEGRA210_DMIC_STATUS_ENABLE_STATUS_SHIFT)
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/* Fields in TEGRA210_DMIC_CTRL */
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#define TEGRA210_DMIC_CTRL_TRIMMER_SEL_SHIFT 12
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#define TEGRA210_DMIC_CTRL_TRIMMER_SEL_MASK (0x1f << TEGRA210_DMIC_CTRL_TRIMMER_SEL_SHIFT)
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#define TEGRA210_DMIC_CTRL_CHANNEL_SELECT_SHIFT 8
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#define TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK (0x3 << TEGRA210_DMIC_CTRL_CHANNEL_SELECT_SHIFT)
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#define TEGRA210_DMIC_CTRL_LRSEL_POLARITY_SHIFT 4
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#define TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK (0x1 << TEGRA210_DMIC_CTRL_LRSEL_POLARITY_SHIFT)
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#define TEGRA210_DMIC_CTRL_OSR_SHIFT 0
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#define TEGRA210_DMIC_CTRL_OSR_MASK (0x3 << TEGRA210_DMIC_CTRL_OSR_SHIFT)
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/* Fields in TEGRA210_DMIC_DBG_CTRL */
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#define TEGRA210_DMIC_DBG_CTRL_DCR_ENABLE BIT(3)
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#define TEGRA210_DMIC_DBG_CTRL_LP_ENABLE BIT(2)
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#define TEGRA210_DMIC_DBG_CTRL_SC_ENABLE BIT(1)
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#define TEGRA210_DMIC_DBG_CTRL_BYPASS BIT(0)
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enum tegra_dmic_ch_select {
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DMIC_CH_SELECT_NONE,
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DMIC_CH_SELECT_LEFT,
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DMIC_CH_SELECT_RIGHT,
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DMIC_CH_SELECT_STEREO,
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};
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struct tegra210_dmic {
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struct clk *clk_dmic;
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struct clk *clk_pll_a_out0;
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struct regmap *regmap;
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struct pinctrl *pinctrl;
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struct pinctrl_state *pin_active_state;
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struct pinctrl_state *pin_idle_state;
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const char *prod_name;
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int boost_gain; /* with 100x factor */
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int ch_select;
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int tx_mono_to_stereo;
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int sample_rate_via_control;
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unsigned int osr_val; /* osr value */
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int lrsel;
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bool is_shutdown;
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int format_out;
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bool set_parent_rate;
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void (*start_capture_cb)(void);
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};
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/* exported functions to enable DMIC from other driver */
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int tegra210_dmic_enable(int id);
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int tegra210_dmic_disable(int id);
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#endif
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