abhinayaa f2653ba797 drivers: pva: Update desc checks for DIM3 ...

When ECET is set to DIM3, descriptor validation should happen as
follows:
 - when SW sequencing is used, or the HW sequencing mode used is
   "descriptor addressing", both ns1 and nd1 should be positive
 - In all other cases, ns1 may be 0, nd1 must be non-zero and greater
   than or equal to ns1.
Update descriptor validation checks accordingly.

Bug 4245426

Change-Id: Ie6ae7e79fd5ea9b5a1345300c6eca5f8b5d283ec
Signed-off-by: abhinayaa <abhinayaa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2988527
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2999161
Reviewed-by: Amruta Sai Anusha Bhamidipati <abhamidipati@nvidia.com>
Reviewed-by: Omar Nemri <onemri@nvidia.com>
Tested-by: Omar Nemri <onemri@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>

2023-10-20 01:26:16 -07:00

..

tegra

drivers: pva: Update desc checks for DIM3

2023-10-20 01:26:16 -07:00