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f23cc48733
This CL creates a dtsi file for display related nodes (dce/display) It also cretes a dtsi file for dcb display blob. Bug 3713048 Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com> Change-Id: I549fd9d78cd4e771d6b8fd893a2d43f2cff83f75 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2795787 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
726 lines
32 KiB
C
726 lines
32 KiB
C
/*
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* Copyright (c) 2018-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* NVIDIA CORPORATION and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA CORPORATION is strictly prohibited.
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*/
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#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_OOT_H
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#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_OOT_H
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/**
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* @file
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* @defgroup bpmp_clock_ids Clock ID's
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* @{
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*/
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */
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#define TEGRA234_CLK_ACTMON 1U
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/** @brief output of gate CLK_ENB_ADSP */
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#define TEGRA234_CLK_ADSP 2U
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/** @brief output of gate CLK_ENB_ADSPNEON */
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#define TEGRA234_CLK_ADSPNEON 3U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
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#define TEGRA234_CLK_AXI_CBB 8U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
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#define TEGRA234_CLK_CAN1 9U
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/** @brief output of gate CLK_ENB_CAN1_HOST */
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#define TEGRA234_CLK_CAN1_HOST 10U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
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#define TEGRA234_CLK_CAN2 11U
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/** @brief output of gate CLK_ENB_CAN2_HOST */
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#define TEGRA234_CLK_CAN2_HOST 12U
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/* free 13 */
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/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
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#define TEGRA234_CLK_CLK_M 14U
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/** @brief output of gate CLK_ENB_DPAUX */
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#define TEGRA234_CLK_DPAUX 19U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG1 */
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#define TEGRA234_CLK_NVJPG1 20U
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/**
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* @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY
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* divided by the divider controlled by ACLK_CLK_DIVISOR in
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* CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER
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*/
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#define TEGRA234_CLK_ACLK 21U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
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#define TEGRA234_CLK_MSS_ENCRYPT 22U
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/** @brief clock recovered from EAVB input */
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#define TEGRA234_CLK_EQOS_RX_INPUT 23U
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/* free 24 */
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
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#define TEGRA234_CLK_AON_APB 25U
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/** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
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#define TEGRA234_CLK_AON_NIC 26U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
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#define TEGRA234_CLK_AON_CPU_NIC 27U
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/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
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#define TEGRA234_CLK_PLLA1 28U
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/**
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* @brief controls the EMC clock frequency.
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* @details Doing a clk_set_rate on this clock will select the
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* appropriate clock source, program the source rate and execute a
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* specific sequence to switch to the new clock source for both memory
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* controllers. This can be used to control the balance between memory
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* throughput and memory controller power.
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*/
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
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#define TEGRA234_CLK_EQOS_AXI 32U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
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#define TEGRA234_CLK_EQOS_PTP_REF 33U
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/** @brief output of gate CLK_ENB_EQOS_RX */
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#define TEGRA234_CLK_EQOS_RX 34U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */
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#define TEGRA234_CLK_EQOS_TX 35U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
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#define TEGRA234_CLK_EXTPERIPH1 36U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
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#define TEGRA234_CLK_EXTPERIPH2 37U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
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#define TEGRA234_CLK_EXTPERIPH3 38U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
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#define TEGRA234_CLK_EXTPERIPH4 39U
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/** @brief output of gate CLK_ENB_FUSE */
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#define TEGRA234_CLK_FUSE 40U
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/** @brief output of GPU GPC0 clkGen (in 1x mode same rate as GPC0 MUX2 out) */
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#define TEGRA234_CLK_GPC0CLK 41U
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/** @brief TODO */
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#define TEGRA234_CLK_GPU_PWR 42U
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
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/* free 43:45 */
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/** @brief xusb_hs_hsicp_clk */
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#define TEGRA234_CLK_XUSB_HS_HSICP 47U
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/* free 68 */
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
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#define TEGRA234_CLK_ISP 69U
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/** @brief Monitored branch of EQOS_RX clock */
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#define TEGRA234_CLK_EQOS_RX_M 70U
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/** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */
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#define TEGRA234_CLK_MAUD 71U
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/** @brief output of gate CLK_ENB_MIPI_CAL */
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#define TEGRA234_CLK_MIPI_CAL 72U
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
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#define TEGRA234_CLK_MPHY_CORE_PLL_FIXED 73U
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/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
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#define TEGRA234_CLK_MPHY_L0_RX_ANA 74U
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/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
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#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT 75U
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/** @brief output of gate CLK_ENB_MPHY_L0_RX_SYMB */
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#define TEGRA234_CLK_MPHY_L0_RX_SYMB 76U
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/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
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#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT 77U
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/** @brief output of gate CLK_ENB_MPHY_L0_TX_SYMB */
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#define TEGRA234_CLK_MPHY_L0_TX_SYMB 78U
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/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
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#define TEGRA234_CLK_MPHY_L1_RX_ANA 79U
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
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#define TEGRA234_CLK_MPHY_TX_1MHZ_REF 80U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
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#define TEGRA234_CLK_NVCSI 81U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
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#define TEGRA234_CLK_NVCSILP 82U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
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#define TEGRA234_CLK_NVDEC 83U
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/** @brief CLK_RST_CONTROLLER_HUBCLK_OUT_SWITCH_DIVIDER switch divider output (hubclk) */
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#define TEGRA234_CLK_HUB 84U
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/** @brief CLK_RST_CONTROLLER_DISPCLK_SWITCH_DIVIDER switch divider output (dispclk) */
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#define TEGRA234_CLK_DISP 85U
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/** @brief RG_CLK_CTRL__0_DIV divider output (nvdisplay_p0_clk) */
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#define TEGRA234_CLK_NVDISPLAY_P0 86U
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/** @brief RG_CLK_CTRL__1_DIV divider output (nvdisplay_p1_clk) */
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#define TEGRA234_CLK_NVDISPLAY_P1 87U
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/** @brief DSC_CLK (DISPCLK ÷ 3) */
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#define TEGRA234_CLK_DSC 88U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
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#define TEGRA234_CLK_NVENC 89U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
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#define TEGRA234_CLK_NVJPG 90U
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/** @brief input from Tegra's XTAL_IN */
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#define TEGRA234_CLK_OSC 91U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH switch divider output */
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#define TEGRA234_CLK_AON_TOUCH 92U
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/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
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#define TEGRA234_CLK_PLLAON 94U
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/* free 95:99 */
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/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
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#define TEGRA234_CLK_PLLE 100U
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/** @brief PLLP vco output */
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#define TEGRA234_CLK_PLLP 101U
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/** Fixed frequency 960MHz PLL for USB and EAVB */
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#define TEGRA234_CLK_UTMIP_PLL 103U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC output */
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#define TEGRA234_CLK_RCE_CPU_NIC 113U
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/** @brief CLK_RST_CONTROLLER_RCE_NIC_RATE divider output */
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#define TEGRA234_CLK_RCE_NIC 114U
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/* free 115:116 */
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW switch divider output */
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#define TEGRA234_CLK_AON_I2C_SLOW 117U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
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#define TEGRA234_CLK_SCE_CPU_NIC 118U
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/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
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#define TEGRA234_CLK_SCE_NIC 119U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
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#define TEGRA234_CLK_SDMMC1 120U
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/** @brief Logical clk for setting the UPHY PLL3 rate */
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#define TEGRA234_CLK_UPHY_PLL3 121U
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/* free 122 */
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */
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#define TEGRA234_CLK_SE 124U
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/** @brief VPLL select for sor0_ref clk driven by disp_2clk_sor0_head_sel signal */
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#define TEGRA234_CLK_SOR0_PLL_REF 125U
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/** @brief Output of mux controlled by disp_2clk_sor0_pll_ref_clk_safe signal (sor0_ref_clk) */
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#define TEGRA234_CLK_SOR0_REF 126U
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/** @brief VPLL select for sor1_ref clk driven by disp_2clk_sor0_head_sel signal */
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#define TEGRA234_CLK_SOR1_PLL_REF 127U
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/** @brief SOR_PLL_REF_CLK_CTRL__0_DIV divider output */
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#define TEGRA234_CLK_PRE_SOR0_REF 128U
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/** @brief Output of mux controlled by disp_2clk_sor1_pll_ref_clk_safe signal (sor1_ref_clk) */
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#define TEGRA234_CLK_SOR1_REF 129U
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/** @brief SOR_PLL_REF_CLK_CTRL__1_DIV divider output */
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#define TEGRA234_CLK_PRE_SOR1_REF 130U
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/** @brief output of gate CLK_ENB_SOR_SAFE */
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#define TEGRA234_CLK_SOR_SAFE 131U
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/** @brief SOR_CLK_CTRL__0_DIV divider output */
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#define TEGRA234_CLK_SOR0_DIV 132U
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/* free 133 */
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
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#define TEGRA234_CLK_DMIC5 134U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
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#define TEGRA234_CLK_SPI1 135U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
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#define TEGRA234_CLK_SPI2 136U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI3 */
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#define TEGRA234_CLK_SPI3 137U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
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#define TEGRA234_CLK_I2C_SLOW 138U
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/** @brief controls MPHY_FORCE_LS_MODE upon enable & disable */
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#define TEGRA234_CLK_MPHY_FORCE_LS_MODE 151U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH0 */
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#define TEGRA234_CLK_TACH0 152U
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
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#define TEGRA234_CLK_TSEC 153U
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */
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#define TEGRA234_CLK_TSEC_PKA 154U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
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#define TEGRA234_CLK_UARTB 156U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
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#define TEGRA234_CLK_UARTC 157U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
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#define TEGRA234_CLK_UARTD 158U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
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#define TEGRA234_CLK_UARTE 159U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
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#define TEGRA234_CLK_UARTF 160U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
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#define TEGRA234_CLK_UART_FST_MIPI_CAL 162U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
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#define TEGRA234_CLK_UFSDEV_REF 163U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
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#define TEGRA234_CLK_UFSHC 164U
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/** @brief output of gate CLK_ENB_USB2_TRK */
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#define TEGRA234_CLK_USB2_TRK 165U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
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#define TEGRA234_CLK_VI 166U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_CSITE switch divider output */
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#define TEGRA234_CLK_CSITE 168U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_IST switch divider output */
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#define TEGRA234_CLK_IST 169U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_IST_JTAG_REG_CLK_SEL */
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#define TEGRA234_CLK_JTAG_INTFC_PRE_CG 170U
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/** @brief dla0_falcon_clk */
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#define TEGRA234_CLK_DLA0_FALCON 174U
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/** @brief dla0_core_clk */
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#define TEGRA234_CLK_DLA0_CORE 175U
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/** @brief dla1_falcon_clk */
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#define TEGRA234_CLK_DLA1_FALCON 176U
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/** @brief dla1_core_clk */
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#define TEGRA234_CLK_DLA1_CORE 177U
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/** @brief Output of mux controlled by disp_2clk_sor0_clk_safe signal (sor0_clk) */
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#define TEGRA234_CLK_SOR0 178U
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/** @brief Output of mux controlled by disp_2clk_sor1_clk_safe signal (sor1_clk) */
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#define TEGRA234_CLK_SOR1 179U
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/** @brief DP macro feedback clock (same as LINKA_SYM CLKOUT) */
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#define TEGRA234_CLK_SOR_PAD_INPUT 180U
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/** @brief Output of mux controlled by disp_2clk_h0_dsi_sel signal in sf0_clk path */
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#define TEGRA234_CLK_PRE_SF0 181U
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/** @brief Output of mux controlled by disp_2clk_sf0_clk_safe signal (sf0_clk) */
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#define TEGRA234_CLK_SF0 182U
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/** @brief Output of mux controlled by disp_2clk_sf1_clk_safe signal (sf1_clk) */
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#define TEGRA234_CLK_SF1 183U
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/** @brief CLKOUT_AB output from DSI BRICK A (dsi_clkout_ab) */
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#define TEGRA234_CLK_DSI_PAD_INPUT 184U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTI switch divider output (uarti_r_clk) */
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#define TEGRA234_CLK_UARTI 188U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ switch divider output (uartj_r_clk) */
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#define TEGRA234_CLK_UARTJ 189U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH switch divider output */
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#define TEGRA234_CLK_UARTH 190U
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/** @brief ungated version of fuse clk */
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#define TEGRA234_CLK_FUSE_SERIAL 191U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST switch divider output */
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#define TEGRA234_CLK_VI_CONST 196U
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/** @brief NAFLL clock source for BPMP */
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#define TEGRA234_CLK_NAFLL_BPMP 197U
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/** @brief NAFLL clock source for SCE */
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#define TEGRA234_CLK_NAFLL_SCE 198U
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/** @brief NAFLL clock source for NVDEC */
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#define TEGRA234_CLK_NAFLL_NVDEC 199U
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/** @brief NAFLL clock source for NVJPG */
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#define TEGRA234_CLK_NAFLL_NVJPG 200U
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/** @brief NAFLL clock source for TSEC */
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#define TEGRA234_CLK_NAFLL_TSEC 201U
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/* RESERVED 202 */
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/** @brief NAFLL clock source for VI */
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#define TEGRA234_CLK_NAFLL_VI 203U
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/** @brief NAFLL clock source for SE */
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#define TEGRA234_CLK_NAFLL_SE 204U
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/** @brief NAFLL clock source for NVENC */
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#define TEGRA234_CLK_NAFLL_NVENC 205U
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/** @brief NAFLL clock source for ISP */
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#define TEGRA234_CLK_NAFLL_ISP 206U
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/** @brief NAFLL clock source for VIC */
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#define TEGRA234_CLK_NAFLL_VIC 207U
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/* free 208 */
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/** @brief NAFLL clock source for AXICBB */
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#define TEGRA234_CLK_NAFLL_AXICBB 209U
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/** @brief NAFLL clock source for NVJPG1 */
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#define TEGRA234_CLK_NAFLL_NVJPG1 210U
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/** @brief NAFLL clock source for PVA core */
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#define TEGRA234_CLK_NAFLL_PVA0_CORE 211U
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/** @brief NAFLL clock source for PVA VPS */
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#define TEGRA234_CLK_NAFLL_PVA0_VPS 212U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0 switch divider output (dbgapb_clk) */
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#define TEGRA234_CLK_DBGAPB 213U
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/** @brief NAFLL clock source for RCE */
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#define TEGRA234_CLK_NAFLL_RCE 214U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_LA switch divider output (la_r_clk) */
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#define TEGRA234_CLK_LA 215U
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/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTD */
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#define TEGRA234_CLK_PLLP_OUT_JTAG 216U
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/** @brief AXI_CBB branch sharing gate control with SDMMC4 */
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#define TEGRA234_CLK_SDMMC4_AXICIF 217U
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/* free 226:228 */
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/** @brief Monitored branch of PEX0_C0_CORE clock */
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#define TEGRA234_CLK_PEX0_C0_CORE_M 229U
|
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/** @brief Monitored branch of PEX0_C1_CORE clock */
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#define TEGRA234_CLK_PEX0_C1_CORE_M 230U
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/** @brief Monitored branch of PEX0_C2_CORE clock */
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#define TEGRA234_CLK_PEX0_C2_CORE_M 231U
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/** @brief Monitored branch of PEX0_C3_CORE clock */
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#define TEGRA234_CLK_PEX0_C3_CORE_M 232U
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/** @brief Monitored branch of PEX0_C4_CORE clock */
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#define TEGRA234_CLK_PEX0_C4_CORE_M 233U
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/** @brief Monitored branch of PEX1_C5_CORE clock */
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#define TEGRA234_CLK_PEX1_C5_CORE_M 234U
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/** @brief Monitored branch of PEX1_C6_CORE clock */
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#define TEGRA234_CLK_PEX1_C6_CORE_M 235U
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/** @brief output of GPU GPC1 clkGen (in 1x mode same rate as GPC1 MUX2 out) */
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#define TEGRA234_CLK_GPC1CLK 236U
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/* free 238 */
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/** @brief PLLC4 VCO followed by DIV3 path */
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#define TEGRA234_CLK_PLLC4_OUT1 239U
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/** @brief PLLC4 VCO followed by DIV5 path */
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#define TEGRA234_CLK_PLLC4_OUT2 240U
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/** @brief output of the mux controlled by PLLC4_CLK_SEL */
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#define TEGRA234_CLK_PLLC4_MUXED 241U
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/** @brief PLLC4 VCO followed by DIV2 path */
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#define TEGRA234_CLK_PLLC4_VCO_DIV2 242U
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/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVHS_BASE */
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#define TEGRA234_CLK_PLLNVHS 243U
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/** @brief Monitored branch of PEX2_C7_CORE clock */
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#define TEGRA234_CLK_PEX2_C7_CORE_M 244U
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/** @brief Monitored branch of PEX2_C8_CORE clock */
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#define TEGRA234_CLK_PEX2_C8_CORE_M 245U
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/** @brief Monitored branch of PEX2_C9_CORE clock */
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#define TEGRA234_CLK_PEX2_C9_CORE_M 246U
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/** @brief Monitored branch of PEX2_C10_CORE clock */
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#define TEGRA234_CLK_PEX2_C10_CORE_M 247U
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/* free 252:253 */
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP switch divider output */
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#define TEGRA234_CLK_PEX_SATA_USB_RX_BYP 254U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT switch divider output */
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#define TEGRA234_CLK_PEX_USB_PAD_PLL0_MGMT 255U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT switch divider output */
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#define TEGRA234_CLK_PEX_USB_PAD_PLL1_MGMT 256U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT switch divider output */
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#define TEGRA234_CLK_PEX_USB_PAD_PLL2_MGMT 257U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT switch divider output */
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#define TEGRA234_CLK_PEX_USB_PAD_PLL3_MGMT 258U
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/* free 259:262 */
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP switch divider output */
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#define TEGRA234_CLK_NVHS_RX_BYP_REF 263U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT switch divider output */
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#define TEGRA234_CLK_NVHS_PLL0_MGMT 264U
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/** @brief xusb_core_dev_clk */
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|
#define TEGRA234_CLK_XUSB_CORE_DEV 265U
|
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST switch divider output */
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|
#define TEGRA234_CLK_XUSB_CORE_MUX 266U
|
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/** @brief xusb_core_host_clk */
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|
#define TEGRA234_CLK_XUSB_CORE_HOST 267U
|
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/** @brief xusb_core_superspeed_clk */
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|
#define TEGRA234_CLK_XUSB_CORE_SS 268U
|
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON switch divider output */
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#define TEGRA234_CLK_XUSB_FALCON 269U
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/** @brief xusb_falcon_host_clk */
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|
#define TEGRA234_CLK_XUSB_FALCON_HOST 270U
|
|
/** @brief xusb_falcon_superspeed_clk */
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|
#define TEGRA234_CLK_XUSB_FALCON_SS 271U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS switch divider output */
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#define TEGRA234_CLK_XUSB_FS 272U
|
|
/** @brief xusb_fs_host_clk */
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#define TEGRA234_CLK_XUSB_FS_HOST 273U
|
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/** @brief xusb_fs_dev_clk */
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|
#define TEGRA234_CLK_XUSB_FS_DEV 274U
|
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS switch divider output */
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#define TEGRA234_CLK_XUSB_SS 275U
|
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/** @brief xusb_ss_dev_clk */
|
|
#define TEGRA234_CLK_XUSB_SS_DEV 276U
|
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/** @brief xusb_ss_superspeed_clk */
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|
#define TEGRA234_CLK_XUSB_SS_SUPERSPEED 277U
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/* free 278:279 */
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/** @brief NAFLL clock source for CPU cluster 0 */
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|
#define TEGRA234_CLK_NAFLL_CLUSTER0 280U /* TODO: remove */
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#define TEGRA234_CLK_NAFLL_CLUSTER0_CORE 280U
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|
/** @brief NAFLL clock source for CPU cluster 1 */
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|
#define TEGRA234_CLK_NAFLL_CLUSTER1 281U /* TODO: remove */
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|
#define TEGRA234_CLK_NAFLL_CLUSTER1_CORE 281U
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|
/** @brief NAFLL clock source for CPU cluster 2 */
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|
#define TEGRA234_CLK_NAFLL_CLUSTER2 282U /* TODO: remove */
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|
#define TEGRA234_CLK_NAFLL_CLUSTER2_CORE 282U
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/* free 283 */
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/** @brief CLK_RST_CONTROLLER_CAN1_CORE_RATE divider output */
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|
#define TEGRA234_CLK_CAN1_CORE 284U
|
|
/** @brief CLK_RST_CONTROLLER_CAN2_CORE_RATE divider outputt */
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#define TEGRA234_CLK_CAN2_CORE 285U
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|
/** @brief CLK_RST_CONTROLLER_PLLA1_OUT1 switch divider output */
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|
#define TEGRA234_CLK_PLLA1_OUT1 286U
|
|
/** @brief NVHS PLL hardware power sequencer (overrides 'manual' programming of PLL) */
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|
#define TEGRA234_CLK_PLLNVHS_HPS 287U
|
|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE */
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|
#define TEGRA234_CLK_PLLREFE_VCOOUT 288U
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|
/* free 290 */
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|
/** @brief Fixed 48MHz clock divided down from utmipll */
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|
#define TEGRA234_CLK_UTMIPLL_CLKOUT48 291U
|
|
/** @brief Fixed 480MHz clock divided down from utmipll */
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|
#define TEGRA234_CLK_UTMIPLL_CLKOUT480 292U
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/* free 293 */
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/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
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|
#define TEGRA234_CLK_PLLNVCSI 294U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI switch divider output */
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|
#define TEGRA234_CLK_PVA0_CPU_AXI 295U
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|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS switch divider output */
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|
#define TEGRA234_CLK_PVA0_VPS 297U
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|
/** @brief DLA0_CORE_NAFLL */
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|
#define TEGRA234_CLK_NAFLL_DLA0_CORE 299U
|
|
/** @brief DLA0_FALCON_NAFLL */
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|
#define TEGRA234_CLK_NAFLL_DLA0_FALCON 300U
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|
/** @brief DLA1_CORE_NAFLL */
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|
#define TEGRA234_CLK_NAFLL_DLA1_CORE 301U
|
|
/** @brief DLA1_FALCON_NAFLL */
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|
#define TEGRA234_CLK_NAFLL_DLA1_FALCON 302U
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|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
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#define TEGRA234_CLK_AON_UART_FST_MIPI_CAL 303U
|
|
/** @brief GPU system clock */
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|
#define TEGRA234_CLK_GPUSYS 304U
|
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 */
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#define TEGRA234_CLK_I2C5 305U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider free running clk */
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|
#define TEGRA234_CLK_FR_SE 306U
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|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC switch divider output */
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|
#define TEGRA234_CLK_BPMP_CPU_NIC 307U
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/** @brief output of gate CLK_ENB_BPMP_CPU */
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|
#define TEGRA234_CLK_BPMP_CPU 308U
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|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSC switch divider output */
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|
#define TEGRA234_CLK_TSC 309U
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|
/** @brief output of mem pll A sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMC */
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#define TEGRA234_CLK_EMCSA_MPLL 310U
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/** @brief output of mem pll B sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB */
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#define TEGRA234_CLK_EMCSB_MPLL 311U
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/** @brief output of mem pll C sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC */
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#define TEGRA234_CLK_EMCSC_MPLL 312U
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/** @brief output of mem pll D sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD */
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#define TEGRA234_CLK_EMCSD_MPLL 313U
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|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
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|
#define TEGRA234_CLK_PLLC 314U
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|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
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#define TEGRA234_CLK_PLLC2 315U
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/* free 326 */
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/** @brief CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER skip divider output */
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#define TEGRA234_CLK_TSC_REF 317U
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|
/** @brief Dummy clock to ensure minimum SoC voltage for fuse burning */
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|
#define TEGRA234_CLK_FUSE_BURN 318U
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|
/** @brief GBE PLL */
|
|
#define TEGRA234_CLK_PLLGBE 319U
|
|
/** @brief GBE PLL hardware power sequencer */
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|
#define TEGRA234_CLK_PLLGBE_HPS 320U
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|
/** @brief output of EMC CDB side A fixed (DIV4) divider */
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|
#define TEGRA234_CLK_EMCSA_EMC 321U
|
|
/** @brief output of EMC CDB side B fixed (DIV4) divider */
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|
#define TEGRA234_CLK_EMCSB_EMC 322U
|
|
/** @brief output of EMC CDB side C fixed (DIV4) divider */
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|
#define TEGRA234_CLK_EMCSC_EMC 323U
|
|
/** @brief output of EMC CDB side D fixed (DIV4) divider */
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|
#define TEGRA234_CLK_EMCSD_EMC 324U
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/* free 325 */
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/** @brief PLLE hardware power sequencer (overrides 'manual' programming of PLL) */
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#define TEGRA234_CLK_PLLE_HPS 326U
|
|
/** @brief CLK_ENB_PLLREFE_OUT gate output */
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|
#define TEGRA234_CLK_PLLREFE_VCOOUT_GATED 327U
|
|
/** @brief TEGRA234_CLK_SOR_SAFE clk source (PLLP_OUT0 divided by 17) */
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|
#define TEGRA234_CLK_PLLP_DIV17 328U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM switch divider output */
|
|
#define TEGRA234_CLK_SOC_THERM 329U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSENSE switch divider output */
|
|
#define TEGRA234_CLK_TSENSE 330U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider free running clk */
|
|
#define TEGRA234_CLK_FR_SEU1 331U
|
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|
/* free 332 */
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|
|
/** @brief NAFLL clock source for OFA */
|
|
#define TEGRA234_CLK_NAFLL_OFA 333U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_OFA switch divider output */
|
|
#define TEGRA234_CLK_OFA 334U
|
|
/** @brief NAFLL clock source for SEU1 */
|
|
#define TEGRA234_CLK_NAFLL_SEU1 335U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider gated output */
|
|
#define TEGRA234_CLK_SEU1 336U
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
|
|
#define TEGRA234_CLK_SPI4 337U
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI5 */
|
|
#define TEGRA234_CLK_SPI5 338U
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DCE_CPU_NIC */
|
|
#define TEGRA234_CLK_DCE_CPU_NIC 339U
|
|
/** @brief output of divider CLK_RST_CONTROLLER_DCE_NIC_RATE */
|
|
#define TEGRA234_CLK_DCE_NIC 340U
|
|
/** @brief NAFLL clock source for DCE */
|
|
#define TEGRA234_CLK_NAFLL_DCE 341U
|
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/** @brief Monitored branch of MPHY_L0_RX_ANA clock */
|
|
#define TEGRA234_CLK_MPHY_L0_RX_ANA_M 342U
|
|
/** @brief Monitored branch of MPHY_L1_RX_ANA clock */
|
|
#define TEGRA234_CLK_MPHY_L1_RX_ANA_M 343U
|
|
/** @brief ungated version of TX symbol clock after fixed 1/2 divider */
|
|
#define TEGRA234_CLK_MPHY_L0_TX_PRE_SYMB 344U
|
|
/** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
|
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#define TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV 345U
|
|
/** @brief output of gate CLK_ENB_MPHY_L0_TX_2X_SYMB */
|
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#define TEGRA234_CLK_MPHY_L0_TX_2X_SYMB 346U
|
|
/** @brief output of SW_MPHY_L0_TX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
|
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#define TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV 347U
|
|
/** @brief output of SW_MPHY_L0_TX_LS_3XBIT divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
|
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#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV 348U
|
|
/** @brief LS/HS divider mux SW_MPHY_L0_TX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
|
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#define TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV 349U
|
|
/** @brief Monitored branch of MPHY_L0_TX_SYMB clock */
|
|
#define TEGRA234_CLK_MPHY_L0_TX_SYMB_M 350U
|
|
/** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
|
|
#define TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV 351U
|
|
/** @brief output of SW_MPHY_L0_RX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
|
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#define TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV 352U
|
|
/** @brief output of SW_MPHY_L0_RX_LS_BIT divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
|
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#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV 353U
|
|
/** @brief LS/HS divider mux SW_MPHY_L0_RX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
|
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#define TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV 354U
|
|
/** @brief Monitored branch of MPHY_L0_RX_SYMB clock */
|
|
#define TEGRA234_CLK_MPHY_L0_RX_SYMB_M 355U
|
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|
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/* free 356 */
|
|
|
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH1 */
|
|
#define TEGRA234_CLK_TACH1 365U
|
|
/** @brief GBE_UPHY_MGBES_APP_CLK switch divider gated output */
|
|
#define TEGRA234_CLK_MGBES_APP 366U
|
|
/** @brief Logical clk for setting GBE UPHY PLL2 TX_REF rate */
|
|
#define TEGRA234_CLK_UPHY_GBE_PLL2_TX_REF 367U
|
|
/** @brief Logical clk for setting GBE UPHY PLL2 XDIG rate */
|
|
#define TEGRA234_CLK_UPHY_GBE_PLL2_XDIG 368U
|
|
/** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate ouput */
|
|
#define TEGRA234_CLK_MGBE1_MACSEC 387U
|
|
/** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate ouput */
|
|
#define TEGRA234_CLK_MGBE2_MACSEC 396U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_RX_BYP switch divider output */
|
|
#define TEGRA234_CLK_GBE_RX_BYP_REF 409U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL0_MGMT switch divider output */
|
|
#define TEGRA234_CLK_GBE_PLL0_MGMT 410U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL1_MGMT switch divider output */
|
|
#define TEGRA234_CLK_GBE_PLL1_MGMT 411U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL2_MGMT switch divider output */
|
|
#define TEGRA234_CLK_GBE_PLL2_MGMT 412U
|
|
/** @brief output of gate CLK_ENB_EQOS_MACSEC_RX */
|
|
#define TEGRA234_CLK_EQOS_MACSEC_RX 413U
|
|
/** @brief output of gate CLK_ENB_EQOS_MACSEC_TX */
|
|
#define TEGRA234_CLK_EQOS_MACSEC_TX 414U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider ungated output */
|
|
#define TEGRA234_CLK_EQOS_TX_DIVIDER 415U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL1_MGMT switch divider output */
|
|
#define TEGRA234_CLK_NVHS_PLL1_MGMT 416U
|
|
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EMCHUB mux output */
|
|
#define TEGRA234_CLK_EMCHUB 417U
|
|
/** @brief clock recovered from I2S7 input */
|
|
#define TEGRA234_CLK_I2S7_SYNC_INPUT 418U
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S7 */
|
|
#define TEGRA234_CLK_SYNC_I2S7 419U
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S7 */
|
|
#define TEGRA234_CLK_I2S7 420U
|
|
/** @brief Monitored output of I2S7 pad macro mux */
|
|
#define TEGRA234_CLK_I2S7_PAD_M 421U
|
|
/** @brief clock recovered from I2S8 input */
|
|
#define TEGRA234_CLK_I2S8_SYNC_INPUT 422U
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S8 */
|
|
#define TEGRA234_CLK_SYNC_I2S8 423U
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S8 */
|
|
#define TEGRA234_CLK_I2S8 424U
|
|
/** @brief Monitored output of I2S8 pad macro mux */
|
|
#define TEGRA234_CLK_I2S8_PAD_M 425U
|
|
/** @brief NAFLL clock source for GPU GPC0 */
|
|
#define TEGRA234_CLK_NAFLL_GPC0 426U
|
|
/** @brief NAFLL clock source for GPU GPC1 */
|
|
#define TEGRA234_CLK_NAFLL_GPC1 427U
|
|
/** @brief NAFLL clock source for GPU SYSCLK */
|
|
#define TEGRA234_CLK_NAFLL_GPUSYS 428U
|
|
/** @brief NAFLL clock source for CPU cluster 0 DSUCLK */
|
|
#define TEGRA234_CLK_NAFLL_DSU0 429U /* TODO: remove */
|
|
#define TEGRA234_CLK_NAFLL_CLUSTER0_DSU 429U
|
|
/** @brief NAFLL clock source for CPU cluster 1 DSUCLK */
|
|
#define TEGRA234_CLK_NAFLL_DSU1 430U /* TODO: remove */
|
|
#define TEGRA234_CLK_NAFLL_CLUSTER1_DSU 430U
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/** @brief NAFLL clock source for CPU cluster 2 DSUCLK */
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#define TEGRA234_CLK_NAFLL_DSU2 431U /* TODO: remove */
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#define TEGRA234_CLK_NAFLL_CLUSTER2_DSU 431U
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/** @brief output of gate CLK_ENB_SCE_CPU */
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#define TEGRA234_CLK_SCE_CPU 432U
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/** @brief output of gate CLK_ENB_RCE_CPU */
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#define TEGRA234_CLK_RCE_CPU 433U
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/** @brief output of gate CLK_ENB_DCE_CPU */
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#define TEGRA234_CLK_DCE_CPU 434U
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/** @brief DSIPLL VCO output */
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#define TEGRA234_CLK_DSIPLL_VCO 435U
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/** @brief DSIPLL SYNC_CLKOUTP/N differential output */
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#define TEGRA234_CLK_DSIPLL_CLKOUTPN 436U
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/** @brief DSIPLL SYNC_CLKOUTA output */
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#define TEGRA234_CLK_DSIPLL_CLKOUTA 437U
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/** @brief SPPLL0 VCO output */
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#define TEGRA234_CLK_SPPLL0_VCO 438U
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/** @brief SPPLL0 SYNC_CLKOUTP/N differential output */
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#define TEGRA234_CLK_SPPLL0_CLKOUTPN 439U
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/** @brief SPPLL0 SYNC_CLKOUTA output */
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#define TEGRA234_CLK_SPPLL0_CLKOUTA 440U
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/** @brief SPPLL0 SYNC_CLKOUTB output */
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#define TEGRA234_CLK_SPPLL0_CLKOUTB 441U
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/** @brief SPPLL0 CLKOUT_DIVBY10 output */
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#define TEGRA234_CLK_SPPLL0_DIV10 442U
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/** @brief SPPLL0 CLKOUT_DIVBY25 output */
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#define TEGRA234_CLK_SPPLL0_DIV25 443U
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/** @brief SPPLL0 CLKOUT_DIVBY27P/N differential output */
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#define TEGRA234_CLK_SPPLL0_DIV27PN 444U
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/** @brief SPPLL1 VCO output */
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#define TEGRA234_CLK_SPPLL1_VCO 445U
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/** @brief SPPLL1 SYNC_CLKOUTP/N differential output */
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#define TEGRA234_CLK_SPPLL1_CLKOUTPN 446U
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/** @brief SPPLL1 CLKOUT_DIVBY27P/N differential output */
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#define TEGRA234_CLK_SPPLL1_DIV27PN 447U
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/** @brief VPLL0 reference clock */
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#define TEGRA234_CLK_VPLL0_REF 448U
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/** @brief VPLL0 */
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#define TEGRA234_CLK_VPLL0 449U
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/** @brief VPLL1 */
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#define TEGRA234_CLK_VPLL1 450U
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/** @brief NVDISPLAY_P0_CLK reference select */
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#define TEGRA234_CLK_NVDISPLAY_P0_REF 451U
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/** @brief RG0_PCLK */
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#define TEGRA234_CLK_RG0 452U
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/** @brief RG1_PCLK */
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#define TEGRA234_CLK_RG1 453U
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/** @brief DISPPLL output */
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#define TEGRA234_CLK_DISPPLL 454U
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/** @brief DISPHUBPLL output */
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#define TEGRA234_CLK_DISPHUBPLL 455U
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/** @brief CLK_RST_CONTROLLER_DSI_LP_SWITCH_DIVIDER switch divider output (dsi_lp_clk) */
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#define TEGRA234_CLK_DSI_LP 456U
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/** @brief SWITCH_DSI_CORE_PIXEL_MISC_DSI_CORE_CLK_SRC switch output (dsi_core_clk) */
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#define TEGRA234_CLK_DSI_CORE 459U
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/** @brief Output of mux controlled by pkt_wr_fifo_signal from dsi (dsi_pixel_clk) */
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#define TEGRA234_CLK_DSI_PIXEL 460U
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/** @brief Output of mux controlled by disp_2clk_sor0_dp_sel (pre_sor0_clk) */
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#define TEGRA234_CLK_PRE_SOR0 461U
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/** @brief Output of mux controlled by disp_2clk_sor1_dp_sel (pre_sor1_clk) */
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#define TEGRA234_CLK_PRE_SOR1 462U
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/** @brief CLK_RST_CONTROLLER_LINK_REFCLK_CFG__0 output */
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#define TEGRA234_CLK_DP_LINK_REF 463U
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/** @brief Link clock input from DP macro brick PLL */
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#define TEGRA234_CLK_SOR_LINKA_INPUT 464U
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/** @brief SOR AFIFO clock outut */
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#define TEGRA234_CLK_SOR_LINKA_AFIFO 465U
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/** @brief Monitored branch of linka_afifo_clk */
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#define TEGRA234_CLK_SOR_LINKA_AFIFO_M 466U
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/** @brief Monitored branch of rg0_pclk */
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#define TEGRA234_CLK_RG0_M 467U
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/** @brief Monitored branch of rg1_pclk */
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#define TEGRA234_CLK_RG1_M 468U
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/** @brief Monitored branch of sor0_clk */
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#define TEGRA234_CLK_SOR0_M 469U
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/** @brief Monitored branch of sor1_clk */
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#define TEGRA234_CLK_SOR1_M 470U
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/** @brief EMC PLLHUB output */
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#define TEGRA234_CLK_PLLHUB 471U
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/** @brief output of fixed (DIV2) MC HUB divider */
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#define TEGRA234_CLK_MCHUB 472U
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/** @brief output of divider controlled by EMC side A MC_EMC_SAFE_SAME_FREQ */
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#define TEGRA234_CLK_EMCSA_MC 473U
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/** @brief output of divider controlled by EMC side B MC_EMC_SAFE_SAME_FREQ */
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#define TEGRA234_CLK_EMCSB_MC 474U
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/** @brief output of divider controlled by EMC side C MC_EMC_SAFE_SAME_FREQ */
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#define TEGRA234_CLK_EMCSC_MC 475U
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/** @brief output of divider controlled by EMC side D MC_EMC_SAFE_SAME_FREQ */
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#define TEGRA234_CLK_EMCSD_MC 476U
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#define TEGRA234_MAX_PUBLIC_CLK_ID 476U
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/** @} */
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/* Alias between CAR clock and IP clock names for client conveniency */
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#define TEGRA234_CLK_JTAG_INTFC TEGRA234_CLK_FUSE
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#endif
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