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62dbefc85b
Fix the DSPK DUMMY macro value as driver now supports single cpu multiple codec dais Bug 3772918 Change-Id: Id970db1bc80d210e7bc8e9b687556abeae2683a9 Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/tegra/+/2805825 (cherry picked from commit 289d19d9bb13b423218aaaeae26750dce3706463) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2815762 Reviewed-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Sharad Gupta <sharadg@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
312 lines
6.9 KiB
C
312 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2019-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#ifndef __DT_TEGRA_ASOC_DAIS_H
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#define __DT_TEGRA_ASOC_DAIS_H
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/*
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* DAI links can have one of these value
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* PCM_LINK : optional, if nothing is specified link is treated as PCM link
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* COMPR_LINK : required, if link is used with compress device
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* C2C_LINK : required, for any other back end codec-to-codec links
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*/
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#define PCM_LINK 0
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#define COMPR_LINK 1
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#define C2C_LINK 2
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/*
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* Following DAI indices are derived from respective module drivers.
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* Thus below values have to be in sync with the DAI arrays defined
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* in the drivers.
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*/
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/* common XBAR dais */
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#define XBAR_ADMAIF1 0
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#define XBAR_ADMAIF2 1
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#define XBAR_ADMAIF3 2
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#define XBAR_ADMAIF4 3
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#define XBAR_ADMAIF5 4
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#define XBAR_ADMAIF6 5
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#define XBAR_ADMAIF7 6
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#define XBAR_ADMAIF8 7
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#define XBAR_ADMAIF9 8
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#define XBAR_ADMAIF10 9
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#define XBAR_I2S1 10
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#define XBAR_I2S2 11
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#define XBAR_I2S3 12
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#define XBAR_I2S4 13
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#define XBAR_I2S5 14
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#define XBAR_SFC1 15
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#define XBAR_SFC2 16
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#define XBAR_SFC3 17
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#define XBAR_SFC4 18
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#define XBAR_MIXER_IF1 19
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#define XBAR_MIXER_IF2 20
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#define XBAR_MIXER_IF3 21
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#define XBAR_MIXER_IF4 22
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#define XBAR_MIXER_IF5 23
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#define XBAR_MIXER_IF6 24
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#define XBAR_MIXER_IF7 25
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#define XBAR_MIXER_IF8 26
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#define XBAR_MIXER_IF9 27
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#define XBAR_MIXER_IF10 28
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#define XBAR_AFC1 29
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#define XBAR_AFC2 30
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#define XBAR_AFC3 31
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#define XBAR_AFC4 32
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#define XBAR_AFC5 33
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#define XBAR_AFC6 34
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#define XBAR_OPE1 35
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#define XBAR_SPKPROT 36
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#define XBAR_MVC1 37
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#define XBAR_MVC2 38
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#define XBAR_IQC1_1 39
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#define XBAR_IQC1_2 40
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#define XBAR_IQC2_1 41
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#define XBAR_IQC2_2 42
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#define XBAR_DMIC1 43
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#define XBAR_DMIC2 44
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#define XBAR_DMIC3 45
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#define XBAR_AMX1_OUT 46
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#define XBAR_AMX1_IN1 47
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#define XBAR_AMX1_IN2 48
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#define XBAR_AMX1_IN3 49
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#define XBAR_AMX1_IN4 50
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#define XBAR_AMX2_OUT 51
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#define XBAR_AMX2_IN1 52
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#define XBAR_AMX2_IN2 53
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#define XBAR_AMX2_IN3 54
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#define XBAR_AMX2_IN4 55
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#define XBAR_ADX1_OUT1 56
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#define XBAR_ADX1_OUT2 57
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#define XBAR_ADX1_OUT3 58
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#define XBAR_ADX1_OUT4 59
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#define XBAR_ADX1_IN 60
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#define XBAR_ADX2_OUT1 61
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#define XBAR_ADX2_OUT2 62
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#define XBAR_ADX2_OUT3 63
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#define XBAR_ADX2_OUT4 64
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#define XBAR_ADX2_IN 65
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/* Tegra210 specific XBAR DAIs */
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#define XBAR_OPE2 66
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/* Tegra186 specific XBAR DAIs */
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#define XBAR_ADMAIF11 66
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#define XBAR_ADMAIF12 67
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#define XBAR_ADMAIF13 68
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#define XBAR_ADMAIF14 69
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#define XBAR_ADMAIF15 70
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#define XBAR_ADMAIF16 71
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#define XBAR_ADMAIF17 72
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#define XBAR_ADMAIF18 73
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#define XBAR_ADMAIF19 74
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#define XBAR_ADMAIF20 75
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#define XBAR_I2S6 76
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#define XBAR_AMX3_OUT 77
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#define XBAR_AMX3_IN1 78
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#define XBAR_AMX3_IN2 79
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#define XBAR_AMX3_IN3 80
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#define XBAR_AMX3_IN4 81
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#define XBAR_AMX4_OUT 82
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#define XBAR_AMX4_IN1 83
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#define XBAR_AMX4_IN2 84
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#define XBAR_AMX4_IN3 85
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#define XBAR_AMX4_IN4 86
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#define XBAR_ADX3_OUT1 87
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#define XBAR_ADX3_OUT2 88
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#define XBAR_ADX3_OUT3 89
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#define XBAR_ADX3_OUT4 90
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#define XBAR_ADX3_IN 91
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#define XBAR_ADX4_OUT1 92
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#define XBAR_ADX4_OUT2 93
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#define XBAR_ADX4_OUT3 94
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#define XBAR_ADX4_OUT4 95
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#define XBAR_ADX4_IN 96
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#define XBAR_DMIC4 97
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#define XBAR_ASRC_IF1 98
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#define XBAR_ASRC_IF2 99
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#define XBAR_ASRC_IF3 100
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#define XBAR_ASRC_IF4 101
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#define XBAR_ASRC_IF5 102
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#define XBAR_ASRC_IF6 103
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#define XBAR_ASRC_IF7 104
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#define XBAR_ARAD 105
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#define XBAR_DSPK1 106
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#define XBAR_DSPK2 107
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/* common ADMAIF DAIs */
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#define ADMAIF1 0
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#define ADMAIF2 1
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#define ADMAIF3 2
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#define ADMAIF4 3
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#define ADMAIF5 4
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#define ADMAIF6 5
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#define ADMAIF7 6
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#define ADMAIF8 7
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#define ADMAIF9 8
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#define ADMAIF10 9
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/* Tegra186 specific ADMAIF DAIs */
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#define ADMAIF11 10
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#define ADMAIF12 11
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#define ADMAIF13 12
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#define ADMAIF14 13
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#define ADMAIF15 14
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#define ADMAIF16 15
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#define ADMAIF17 16
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#define ADMAIF18 17
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#define ADMAIF19 18
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#define ADMAIF20 19
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/*
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* ADMAIF_FIFO: DAIs used for DAI links between ADMAIF and ADSP.
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* Offset depends on the number of ADMAIF channels for a chip.
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* The DAI indices for these are derived from below offsets.
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*/
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#define TEGRA210_ADMAIF_FIFO_OFFSET 10
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#define TEGRA186_ADMAIF_FIFO_OFFSET 20
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/*
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* ADMAIF_CIF: DAIs used for codec-to-codec links between ADMAIF and XBAR.
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* Offset depends on the number of ADMAIF channels for a chip.
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* The DAI indices for these are derived from below offsets.
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*/
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#define TEGRA210_ADMAIF_CIF_OFFSET 20
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#define TEGRA186_ADMAIF_CIF_OFFSET 40
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/* I2S */
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#define I2S_CIF 0
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#define I2S_DAP 1
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#define I2S_DUMMY 2
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/* DMIC */
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#define DMIC_CIF 0
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#define DMIC_DAP 1
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#define DMIC_DUMMY 2
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/* DSPK */
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#define DSPK_CIF 0
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#define DSPK_DAP 1
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#define DSPK_DUMMY 2
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/* SFC */
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#define SFC_IN 0
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#define SFC_OUT 1
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/* MIXER */
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#define MIXER_IN1 0
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#define MIXER_IN2 1
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#define MIXER_IN3 2
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#define MIXER_IN4 3
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#define MIXER_IN5 4
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#define MIXER_IN6 5
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#define MIXER_IN7 6
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#define MIXER_IN8 7
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#define MIXER_IN9 8
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#define MIXER_IN10 9
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#define MIXER_OUT1 10
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#define MIXER_OUT2 11
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#define MIXER_OUT3 12
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#define MIXER_OUT4 13
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#define MIXER_OUT5 14
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/* AFC */
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#define AFC_IN 0
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#define AFC_OUT 1
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/* OPE */
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#define OPE_IN 0
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#define OPE_OUT 1
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/* MVC */
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#define MVC_IN 0
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#define MVC_OUT 1
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/* AMX */
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#define AMX_IN1 0
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#define AMX_IN2 1
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#define AMX_IN3 2
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#define AMX_IN4 3
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#define AMX_OUT 4
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/* ADX */
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#define ADX_OUT1 0
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#define ADX_OUT2 1
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#define ADX_OUT3 2
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#define ADX_OUT4 3
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#define ADX_IN 4
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/* ASRC */
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#define ASRC_IN1 0
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#define ASRC_IN2 1
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#define ASRC_IN3 2
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#define ASRC_IN4 3
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#define ASRC_IN5 4
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#define ASRC_IN6 5
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#define ASRC_IN7 6
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#define ASRC_OUT1 7
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#define ASRC_OUT2 8
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#define ASRC_OUT3 9
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#define ASRC_OUT4 10
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#define ASRC_OUT5 11
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#define ASRC_OUT6 12
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/* ARAD */
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#define ARAD 0
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/* ADSP */
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#define ADSP_FE1 0
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#define ADSP_FE2 1
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#define ADSP_FE3 2
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#define ADSP_FE4 3
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#define ADSP_FE5 4
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#define ADSP_FE6 5
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#define ADSP_FE7 6
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#define ADSP_FE8 7
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#define ADSP_FE9 8
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#define ADSP_FE10 9
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#define ADSP_FE11 10
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#define ADSP_FE12 11
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#define ADSP_FE13 12
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#define ADSP_FE14 13
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#define ADSP_FE15 14
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#define ADSP_EAVB_CODEC 15
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#define ADSP_ADMAIF1 16
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#define ADSP_ADMAIF2 17
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#define ADSP_ADMAIF3 18
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#define ADSP_ADMAIF4 19
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#define ADSP_ADMAIF5 20
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#define ADSP_ADMAIF6 21
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#define ADSP_ADMAIF7 22
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#define ADSP_ADMAIF8 23
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#define ADSP_ADMAIF9 24
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#define ADSP_ADMAIF10 25
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#define ADSP_ADMAIF11 26
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#define ADSP_ADMAIF12 27
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#define ADSP_ADMAIF13 28
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#define ADSP_ADMAIF14 29
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#define ADSP_ADMAIF15 30
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#define ADSP_ADMAIF16 31
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#define ADSP_ADMAIF17 32
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#define ADSP_ADMAIF18 33
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#define ADSP_ADMAIF19 34
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#define ADSP_ADMAIF20 35
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#define ADSP_PCM1 36
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#define ADSP_PCM2 37
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#define ADSP_PCM3 38
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#define ADSP_PCM4 39
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#define ADSP_PCM5 40
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#define ADSP_PCM6 41
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#define ADSP_PCM7 42
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#define ADSP_PCM8 43
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#define ADSP_PCM9 44
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#define ADSP_PCM10 45
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#define ADSP_PCM11 46
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#define ADSP_PCM12 47
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#define ADSP_PCM13 48
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#define ADSP_PCM14 49
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#define ADSP_PCM15 50
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#define ADSP_COMPR1 51
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#define ADSP_COMPR2 52
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#define ADSP_EAVB 53
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#endif
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