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c2bf51b5fe
Add Device Tree binding document for the NVIDIA Tegra PEX pad controller. Bug 3621816 Change-Id: I6df186f88c5ea48242472a2c30288d9d0942e679 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2704360 GVS: Gerrit_Virtual_Submit
73 lines
1.8 KiB
YAML
73 lines
1.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/pinctrl-tegra194-pexclk-padctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra PEX pad controller.
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maintainers:
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- Laxman Dewangan <ldewangan@nvidia.com>
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description:
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Bindings for NVIDIA Tegra PEX pad controller.
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properties:
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compatible:
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const: nvidia,tegra194-pexclk-padctl
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reg:
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items:
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- description: Base address and size of the MISC controller.
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- description: Base address and size of the PMC controller.
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required:
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- compatible
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- reg
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patternProperties:
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'pinmux-[0-9]*$':
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type: object
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patternProperties:
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'-pins*$':
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type: object
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description: |
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A pinctrl node should contain at least one subnodes representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured either in display or i2c mode.
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$ref: "/schemas/pinctrl/pincfg-node.yaml"
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properties:
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nvidia,pexclk-single-en:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Enable/disable the pex clock in the pad or not. 1 for enable and 0 for disable.
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pins:
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enum: [ pexclk ]
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description:
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Name of pins.
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pinctrl@3790000 {
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compatible = "nvidia,tegra194-pexclk-padctl";
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reg = <0x0 0x03790000 0x0 0x1000>,
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<0x0 0x037a0000 0x0 0x1000>;
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pexclk_default: pinmux-0 {
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pexclk-pins {
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pins = "pexclk";
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nvidia,pexclk-single-en = <1>;
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};
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};
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};
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};
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...
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