mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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915f2bfa4d
Unifying ADSP driver across t186, t210. This removes the use of chip specific configs. Based on: platform: nvadsp: Enable ADSP in T210 for 4.4 nvadsp: Add nvadsp_os_init for t18x HV config tegra: t210: nvadsp: move hwmbox to chip data platform: nvadsp: Add callbacks to chip data platform: nvadsp: Use WDT irq from chip data soc: adsp: use soc/tegra/chip-id.h for soc header tegra: nvadsp: remove clk periph reset assert/deassert tegra: nvadsp: use ACLK to manage ADSP clk on t186 tegra: nvadsp: dfs: fix tfreq in error path platform: tegra: adsp: update rpm error handling platform: nvadsp: export symbols for audio driver Bug 200272977 Jira EMA-373 Bug 200257350 Bug 200124772 Bug 200289390 Change-Id: Iab20f54a48c67febd6b4ccfaf2e89e5b264e0f5a Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/1468351 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537319 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
145 lines
3.8 KiB
C
145 lines
3.8 KiB
C
/*
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* Copyright (C) 2016-2017 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include "dev-t18x.h"
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#define AST_CONTROL 0x000
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#define AST_STREAMID_CTL_0 0x020
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#define AST_STREAMID_CTL_1 0x024
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#define AST_RGN_SLAVE_BASE_LO 0x100
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#define AST_RGN_SLAVE_BASE_HI 0x104
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#define AST_RGN_MASK_BASE_LO 0x108
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#define AST_RGN_MASK_BASE_HI 0x10c
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#define AST_RGN_MASTER_BASE_LO 0x110
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#define AST_RGN_MASTER_BASE_HI 0x114
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#define AST_RGN_CONTOL 0x118
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#define AST_PAGE_MASK (~0xFFF)
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#define AST_LO_SHIFT 32
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#define AST_LO_MASK 0xFFFFFFFF
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#define AST_PHY_SID_IDX 0
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#define AST_APE_SID_IDX 1
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#define AST_NS (1 << 3)
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#define AST_VMINDEX(IDX) (IDX << 15)
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#define AST_RGN_ENABLE (1 << 0)
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#define AST_RGN_OFFSET 0x20
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struct acast_region {
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u64 rgn;
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u64 rgn_ctrl;
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u64 slave;
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u64 size;
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u64 master;
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};
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#define ACAST_REGIONS 1
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#define ACAST_BASE 0x02994000
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#define ACAST_SIZE 0x1FFF
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#define ACAST_GLOBAL_CTRL_VAL 0x07b80009
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#define ACAST_STREAMID_CTL_0_VAL 0x00007f01
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#define ACAST_STREAMID_CTL_1_VAL 0x00001e01
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static struct acast_region acast_regions[ACAST_REGIONS] = {
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{
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0x2,
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0x00008008,
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0x40000000,
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0x20000000,
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0x40000000,
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},
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};
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static void __iomem *acast_base;
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static inline void acast_write(void __iomem *acast, u32 reg, u32 val)
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{
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writel(val, acast + reg);
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}
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static inline u32 __maybe_unused acast_read(void __iomem *acast, u32 reg)
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{
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return readl(acast + reg);
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}
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static inline u32 acast_rgn_reg(u32 rgn, u32 reg)
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{
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return rgn * AST_RGN_OFFSET + reg;
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}
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static void tegra18x_acast_map(void __iomem *acast, u64 rgn, u64 rgn_ctrl,
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u64 slave, u64 size, u64 master)
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{
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u32 val;
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val = (slave & AST_LO_MASK) | AST_RGN_ENABLE;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_SLAVE_BASE_LO), val);
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val = slave >> AST_LO_SHIFT;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_SLAVE_BASE_HI), val);
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val = master & AST_LO_MASK;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_MASTER_BASE_LO), val);
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val = master >> AST_LO_SHIFT;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_MASTER_BASE_HI), val);
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val = ((size - 1) & AST_PAGE_MASK) & AST_LO_MASK;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_MASK_BASE_LO), val);
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val = (size - 1) >> AST_LO_SHIFT;
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_MASK_BASE_HI), val);
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acast_write(acast,
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acast_rgn_reg(rgn, AST_RGN_CONTOL), rgn_ctrl);
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}
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int nvadsp_acast_init(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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int i;
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if (!acast_base) {
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acast_base = devm_ioremap_nocache(dev, ACAST_BASE, ACAST_SIZE);
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if (IS_ERR_OR_NULL(acast_base)) {
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dev_err(dev, "failed to map ACAST\n");
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return PTR_ERR(acast_base);
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}
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}
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for (i = 0; i < ACAST_REGIONS; i++) {
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tegra18x_acast_map(acast_base,
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acast_regions[i].rgn,
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acast_regions[i].rgn_ctrl,
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acast_regions[i].slave,
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acast_regions[i].size,
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acast_regions[i].master);
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dev_dbg(dev, "i:%d rgn:0x%llx rgn_ctrl:0x%llx ",
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i, acast_regions[i].rgn, acast_regions[i].rgn_ctrl);
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dev_dbg(dev, "slave:0x%llx size:0x%llx master:0x%llx\n",
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acast_regions[i].slave, acast_regions[i].size,
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acast_regions[i].master);
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}
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return 0;
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}
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